Computer Hardware Flashcards
CPUs and device _______ are connected through a common bus to a _______ memory
controllers, shared
What is a uniprocessor?
one processor with a single core
High _____ is important for a uniprocessor
frequency
Pre early 2000’s, ______ doubled in processors every 18 months
frequency
Post 2005, ______ ____ doubled in processors every 18 months
core count
What is a multicore processor?
one processor with multiple cores
A multicore processor contains both shared and core-private ______
caches
________ allows a core to execute more than one thread
hyper-threading
Multiple threads on one core still share caches, ______, etc
registers
Extra threads from hyper threading show up to the OS as additional _____ or ___
cores, CPUs
Mainstream servers using a multisocket motherboard usually have - sockets
2, 4
What does NUMA stand for?
Non-Uniform Memory Access
What is a NUMA node?
A processor and its local memory
Accessing _____ memory is faster than _____ memory in other NUMA nodes. This is known as the NUMA effect.
local, remote
An _________ is a communication medium that connect processors to processors or processors to memory in NUMA nodes
Interconnect
What does numactl do?
Control NUMA policy for processes or shared memory
What does htop do?
Interactive process viewer
What is Moore’s law?
the principle that the speed and capability of computers can be expected to double every two years, as a result of increases in the number of transistors a microchip can contain
Parallelism is offered by ______ ______ and ________
Hyper threading, Multi-core and multi-socket
What are the seven layers in the memory/storage hierarchy. (smallest to biggest)
Registers, L1, L2, L3, Main memory, Persistent memory, Flash/disk
The lower levels of the storage hierarchy contains the ______ of higher levels
contents
____, __, __, __ are examples of volatile SRAM
Registers, L1, L2, L3
Volatile DRAM is ______ memory
main
The _______ ______ points to the next instruction to execute
program counter
Instructions and data moved between cache and memory in ______ ____ units
cache line
Describe the fetch, decode, execute cycle in a CPU
- Fetch next instruction: Instruction contains op-code and possibly data
- Decode op-code
- Execute op-code (using data if necessary)
Opcode instruction can include accessing data and moving between memory and _______
registers
______ are 100x faster than main memory
registers
What is the processor-memory gap?
CPU must bring data from memory to caches to registers
L1 and L2 caches are typically _______
core-local
___ cache is typically shared among all cores
L3
There are many more cache lines of memory than there are ____in the cache
slots
Cache lines are manage by a mapping function and _______ algorithm
replacement
What does DRAM stand for?
dynamic random access memory
What does it mean for memory to be volatile?
contents lost when power is out
____ is used to hold basic information like the BIOS
ROM
What is the basic building black of NAND flash memory?
floating gate transistors
In NAND flash memory, the cells are organized in _____ and _____
blocks, pages
In NAND flash memory, data can be written/read at the ____ level, while modifications must erase the _____
page, block
What is a disadvantage of NAND flash memory?
Cell wears out (dies) after a certain number of erases
How many threshold voltages does a multi-level cell for flash memory have?
3
SSDs imitate the same interface as _____
disks
The _____ ______ ______ (FTL) Maps flash blocks/pages to hard disk sectors using a mapping table
flash translation layer
The _____ inside SSDs caches data, the FTl mapping table, and sometimes the battery
RAM
Persistent memory is also known as _____ ______ ______ (NVM), ________ _____ ____ (NVRAM), or _______ ______ _____ (SCM)
Non-volatile memory, non-volatile RAM, storage class memory
Persistent memory as ____________ like DRAM and _________ like flash memory
byte-addressable, persistent
Persistent memory types include NVDIMM-_ (which is fast, small, and expensive), NVDIMM-_ (which is slow, large, cheap), and _______DC DIMM (which is balanced)
N, F, Optane
What does df do?
storage usage stats
what does mount do?
Mount existing file systems for access, or show
currently mounted file systems
What does iostat do?
Show storage I/O speeds
what does free do?
Show memory usage
Each device has its own _____
controller
Each device is managed by a device _______
driver
What does a device driver do?
- Software to use the controller
- Provides a uniform interface to the device for OS
- Specific to hardware and the OS using the device
Describe the process for reading a character from the keyboard
•CPU tells the keyboard controller “I need to read”
•By loading registers in the device, using device driver
•Keyboard controller knows “I got a read request”
•By examining the registers
•Keyboard receives a character and stores it in
local buffer. Now the keyboard controller needs to let the CPU know that the operation is finished
•This is done using interrupts
An ______ is a single sent by hardware devices to the CPU
interrupt
An ______ _______ ______ (ISR) (AKA interrupt handlers) stops the CPU from its current work to handle an interrupt
Interrupt service routine
After a CPU executes the ISR, it resumes its _______ job
previous
What is an Interrupt Vector?
A table indexed by device number whose entries contains address to the corresponding ISR
An I/O interrupt is sent when…
the read or write operation is completed or ended in an error
An timer expiry interrupt is sent when…
A regularly scheduled task beings or a task has exceeded its allocated time
An program generated interrupt is sent when…
an instruction causes a hardware error condition (ex divide by 0)
An Hardware failure interrupt is sent when…
hardware fails (ex parity error)
_____ _______ for interrupts is when the CPU waits for an I/O operation to finish before executing other jobs
Busy waiting
What is direct memory access for interrupts?
When a device transfers data from its local buffer directly into main memory.
