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computer architecture Flashcards

1
Q

what is a computer

A

an electronic device for storing and processing data in binary

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2
Q

what is computer architecture

A

set of rules and systems that describe computer systems

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3
Q

von-neuman architecture

A

memory stores both data and instructions

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4
Q

Harvard architecture

A

separate memory for data and instructions therefore they can be accessed simultaneously making it faster and more efficient

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5
Q

what are some negatives of harvard architecture

A

not suited for self-modifying code
requires more memory than von-neuman making it more expensive

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6
Q

what is a positive of harvard architecture

A

allows for more cyber resilience as you cant attack both memory simultaneously

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7
Q

what is modified harvard architecture

A

data and cache are separated internally and a single main memory is visible to programs and users

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8
Q

what are the three ways that you can measure the speed of a cpu

A

clock rate
flops
mips
however none of these are ideal as they dont take input and output speeds into account

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9
Q

clock rate

A

more clicks /s means more instructions executed /s

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10
Q

what is a negative of using the clock rate to measure speed

A

its unfair as different instruction can take a different number of clicks

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11
Q

MIPS

A

millions of instructions /s; a better indication of speed but depends which instructions have been counted

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12
Q

flops

A

floating point operations per second

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13
Q

what is moore’s law

A

the transistor number doubles every two years; poweer and heat problems increase as the clock rate does which is very hard to cool down

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14
Q

what is clustering

A

we can increase performance by linking computers using high speed networks which leads to blade servers
applications can tun across the cluster

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15
Q

what is instruction set architecture

A

the view of the processor that is seen by programs being executed by that particular processor

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16
Q

RISC

A

reduced instruction set computers
small number of instructions
all instruction apart from ldr and str operate on registers
instructions usually take one clock cycle to complete

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17
Q

registers

A

holding areas for data being worked on outside the cpu

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18
Q

what are the main two ways of handling subroutines

A

using stack
saving the value of the pc as the return address

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19
Q

what are the 3 status flags of the alu

A

overflow
zero
negative

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20
Q

what is used to add 2 bits together

A

half adder

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21
Q

why do we need a full adder

A

to add multiple bits together

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22
Q

what is the difference between volatile and non-volatile memory

A

volatile memory erases data once the power is off

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23
Q

what is dynamic memory

A

assigning memory space during runtime

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24
Q

what is a positive and negative of dynamic memory

A

relatively cheaper
slower than static

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25
Q

how are bits stored in dynamic memory

A

by charging and discharging a device consisting of a capacitor controlled by a transistor

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26
Q

how are bits read in dynamic memory

A

by sensing the presence/absence of a stored charge

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27
Q

what is address decoding

A

an address decoder maps the linear address to a specific location in memory

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28
Q

big-endian

A

the location/byte with the lowest memory address holds the most significant value

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29
Q

little endian

A

the location with the lowest memory address holds the least significant value

30
Q

combinational logic

A

used for boolean algebra
outputs are a function of their inputs

31
Q

sequential logic

A

outputs are a function of current inputs and current outputs(state)

32
Q

what is an example of sequential logic and how does it work

A

s-r flip flop
s; set
r; reset
a high pulse on s takes us to the Q = 1 state; set
a high pulse on r takes us the the Q’ = 1 state; reset
s and r cant be high simultaneously

33
Q

what are some limitations of the s-r flip flop

A

must have two inputs ; ideally you would want only one input that resets if its 0
you have no way of saying when to store the data; you would need a signal for this to work practically

34
Q

clocked type d flip flop

A

only has one input; the data
has a latch; a switch which allows us to input

35
Q

how does a master-slave flip flop work

A

made from two type d flip flops forming the master and slave
the master received input signals and determines the next state based on them
the clock signal acts as a trigger for the slave stage; when the signal transitions it enables the slave to copy the state of the master
the slave copies the state of the master which becomes the output for the entire flipflop and remains stable until the next clock trigger

36
Q

what do buses do and what are they made up of

A

connect the elements of von neuman architecture
made up of bundles of wire; each one for one bit

37
Q

address bus

A

runs between the cu and main memory
used to tell main memory to access a specific address
the width corresponds with the amount of addressable memory; 32 bits = 4gb (2^32)

38
Q

data bus

A

carries data around the computer
n bit processor = data bus n bits wide

39
Q

external data buses

A

narrower to reduce the number of external connection and therefore cost

40
Q

what is the purpose of the control unit

A

helps everything in the cpu work together through timing
- it is like a little program in the processor that executes the fde cycle endlessly
- controls and sequences other architectural modules using their respective control lines
- driven by the clock that gives regular timed electrical pulses and ticks

41
Q

how does the cu control the alu and registers (for an instruction taking 2 ticks)

A
  1. the control unit feeds the alu with inputs from two specific registers and tells it which operation to do
  2. the control unit directs the alu’s output to a register (the one with a set latch)
42
Q

how does the cu control main memory ( 2 ticks)

A

the cu uses the mar to send pulses down the address bus to the address decoder and the address bus then finds the address in memory
data goes onto the data bus to the mdr which is now latched

43
Q

what are the 2 ways in which the control unit’s fde cycle can be implemented

A

fsm based and microcode

44
Q

fsm based control unit

A

hard-wired sequential logic
high performance
expensive
hard to evolve

45
Q

microcode control unit

A

a sequence of microinstructions in micro memory
slightly lower performance
more flexible

46
Q

micro-instructions (internal, processor, memory)

A

internal to the processor so its invisible to the programmer
you can jump to selected micro-memory locations
in a microcoded processor each machine instruction is implemented in terms of small a small number of microcoded steps

47
Q

what is pipelining

A

a widely used way to exploit parallelism inside the cu to speed up the fde cycle which is done by splitting the cycle into many substeps

48
Q

what are the 3 types of hazards in the control unit

A

control
data
structural

49
Q

control hazards

A

when the control transfer instruction changes the flow of execution

50
Q

what are the 2 types of data hazards

A

when instruction n depends on the results of n-1
when 2 parts of the pipeline need to access the same data

51
Q

structural hazards

A

when two parts of the pipeline need to access the same piece of hardware

52
Q

what is an effect of hazards in the cu

A

can cause the pipeline to stall and need to flush to continue
- can be v complex
may considerably reduce the speedup

53
Q

what is the role of the I/o system

A

enables the attachment of I/o devices to the processor

54
Q

what is the speed gap challenge

A

I/o devices are often mechanical so they run slower Thant the cpu
we have to ensure that the cpu isnt slowed down when interacting with these devices so we dont waste the cpu cycles

55
Q

what are the 2 issues when it comes to I/o systems

A

speed gap challenge
device diversity

56
Q

what are the 3 categories that fall under the device diversity challenge

A

data - access modes diversity
device specific operations
I/o protocols

57
Q

data - access modes diversity

A

eg. read-only, write only, r/w
accessing the individual byte or the block
accessing randomly/sequentially

58
Q

how does I/o protocols affect device diversity

A

synchronous/asynchronous transmission
may deal with transfer errors when needing to connect to the network/cloud due to longer distances

59
Q

how can device specific operations affect device diversity

A

set the clock time, camera focus, cahnging screen resolution (all unique operations)

60
Q

what are device drivers

A

software plugins inside the os that abstract device diversity by grouping similar types of devices

61
Q

what are some of the functions of device drivers

A

registering the device with the os and initialising
imitating data transfer to/from devices
monitoring status events
managing device/system shutdown
- ensures the os doesn’t shutdown until all data is stored
- ensures the device is left in a safe state

62
Q

what are the 2 classifications of device types

A

character devices; send and receive one byte at a time e.g the keyboard
block devices; send and receive multi-byte blocks at a time which is usually faster e.g. the hard disk

63
Q

how big are the blocks that data is read in on the hard drive

A

512 bytes as that is the size of a sector which is the smaller unit of storage on the hard drive

64
Q

what makes up disk access latency

A

seek time; time taken to move in and out of the cylinder
rational delay; time for the required sector to come around
these are mechanical delays much larger than the cpu

65
Q

what are the 2 types of support for I/o devices

A

isolated I/o
memory-mapped I/o

66
Q

isolated I/o

A

the processor provides dedicated physical pins for connection and instructions for doing I/o operations
suited for simple devices as there’s a fixed set of I/o instructions

67
Q

what is a negative of isolated io

A

dosent help much with device diversity

68
Q

memory-mapped io

A

devices sit within the cpu’s linear memory address space

69
Q

what is a positive and negative of memory-mapped io

A

you dont need dedicated instructions
adds complexity to the device as they need to understand larger addresses and work at memory speeds

70
Q

what can cause io transfer errors

A

electrical noise especially on long cables

71
Q

how can io transfer errors be combatted with an example

A

using error detection; may not correct
parity bits; even/odd parity means an even/odd number of 0s

72
Q

what are two negatives of using parity bits as error checking

A

you lose one column
can only detect one error/even number of errors

digital systems (5 decks)

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