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arm assembly Flashcards

1
Q

instruction set architecture

A

the view of the processor as seen by other programs
stores cpu instructions

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2
Q

what are the 2 architecture paradigms

A

cisc; complex instruction set computer
risc; reduced instruction set computer

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3
Q

cisc

A

complex instruction set computer
loads the architecture itself
improved speed at a lower clock rate fur to parallel crossing pipeline
rich isa; a single instruction excesses several low level operations

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4
Q

risc

A

reduced instruction set computer eg arm
small organised instruction set
simple pipeline and complex software

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5
Q

what are some of the fundamentals of the arm instruction set

A

simple design
doesn’t read the cpu but reads the architecture and sends it to the cpu
can remove capabilities from the cpu so its smaller and more efficient
32 bit architecture
assembler hides details

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6
Q

how many registers does the arm cpu have

A

16

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7
Q

what are the 4 special registers in arm

A

stack pointer; points to the last value pushed onto the stack
link; used by functions
pc; next instruction
cpsr(current program status register); result of the last instruction/maintains the state of the cpu

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8
Q

what is an instruction

A

the most basic part of a program

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9
Q

assembler

A

translates assembly into binary

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10
Q

what are directives and what are some examples of what they do

A

assembler instructions that take actions/change settings
e.g. defines symbols dara regions; controls flows; generates reports; defines assemble parameters

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11
Q

what are the different flags in the 4 most significant bits in the cpsr

A

n bit; negative flag
z bit; zero
c bit; carry
v bit; overflow

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12
Q

what type of memory system does arm use

A

memory mapped

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13
Q

stack and heap

A

dynamic data

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14
Q

text

A

stores machine code programs

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15
Q

heap

A

stores data allocated during runtime

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16
Q

how long is a word

A

4 bytes/32 bits

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17
Q

what are the 3 different addressing modes

A

reg + const; registed + constant used to compute the r/w addresses
reg + reg; eg ldr r0, [r1, r2]
reg + reg &laquo_space;scale; shift the 2nd register parameter and add the first register

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18
Q

what are the 4 parts of memory layout/directives

A

bss; global variables that aren’t initialised
data; initialised static variables
text; executable instructions
rodata; contains constants

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19
Q

what is pipelining

A

a way of exploiting inherent parallelism inside the control unit to speed up the fde cycle

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20
Q

what is a label

A

a symbol that represents an address in memory and stores where something is in the code

21
Q

what is program-relative addressing

A

addresses expressed relative to where they are in the code
uses the pc +/- an offset

22
Q

what is a function

A

a stores subroutine that performs a specific task based on its parameters

23
Q

api

A

application programming interface; defines the interfaces that software programs communicate with eachother at a surface level

24
Q

how does function execution work

A

the caller stores arguments in registers/memory
the caller transfers flow control onto the callee
fucntion call; callee allocates memory for doing work
callee executes sthe function body and stores the result in a register
callee deallocates memory
function return; callee returns control to the caller

25
Q

what are calling conventions

A

a set or rules that function implementation has to follow to ensure interoperability

26
Q

what is a negative of calling conventions

A

it may make your code inefficient

27
Q

what are some positives of calling conventions

A

functions written by different programmers can interoperate
functions compiled by two different compilers can interoperate
a library function by a third party can be used without corrupting state

28
Q

what causes exceptions to occur

A

the program excecutes and an external event by the cpu calls its attention/ when theres an unexpected change in flow control
caused by either hardware or software

29
Q

synchronous exceptions

A

caused by an instruction in the running program e.g. arithmetic instructions; invalid memory address

30
Q

asynchronous exceptions

A

usually relates to io operations
cpu receives the signal then notifies the program of what’s happening so you need to have functions to manage this

31
Q

how are exceptions manages through interrupt handling

A

you break from the fde cycle
the current state of the cycle is saved to the cpu
you run the user code to manage interrupts
the state of the fde cycle is restored

32
Q

exception handlers

A

a set of default exceptions in the cpu

33
Q

nvic

A

nested vector interrupt controller; works as a hardware interrupt scheduler, it knows the priority of each interrupt and decides if it should interrupt the cpu
if it does then it goes through the interrupt handling steps (saving the state of the running program)
allows you to extend the interrupt model and introduce additional interrupts
allows you to queue interrupts whilst processing current interrupts

34
Q

what is the purpose of cpu privilege levels

A

to limit resource access to different processed

35
Q

what are the last 4 bits in the cpsr and what is their purpose

A

i bit; irq flag - disable irq interrupts
f bit; fiq flag - disable fiq interrupts
t bit; thumb flag - disable thumb mode
mode; current execution mode
allow you to control interrupts which you can only access if you have privileges

36
Q

how does exception handling occur with the cpsr

A

store the cpsr into the banked spsr
set execution mode and privilege level based on exception type
disable interrupts using the interrupt mask bits in the cpsr
store the return address into banked lr
pushes other registers onto the stack
branch to the exception function based on the address from the vector table
execute exception handler
copy lr into the pc and the spsr into the cpsr
pop the registers back off the stack

37
Q

why do we need banked registers

A

the exception handler is like a function call and you need to know where to return and preserve the registers
speeds up the process of managing interrupts

38
Q

what are banked registers

A

some registers are saved onto your stack and the rest are copied onto banked registers during an interrupt which saves time when jumping in and out of them

39
Q

what is a supervisor instruction

A

provides a means to switch between user code and os code

40
Q

how does user code access system recourses

A

through the use of system calls

41
Q

what is an in io module

A

moves data between memory and the device interface through an io controller

42
Q

what does an interface do

A

communicates with certain types of devices
makes sure the device is ready for the next batch of data and the host is ready to receive the next batch of data coming from the peripheral device

43
Q

protocols

A

the exact interpretation of the signals (command or data) exchanged between the sender and receiver

44
Q

handshake

A

a protocol exchange where the receiver sends acknowledgement for the command and data sent or indicates that it is ready to receive data

45
Q

how does memory mapped io (mmio) work

A

io devices and memory share the same address space and each device has its own reserved block of memory
because of this data transfers to and from the device involves moving bytes to and from the memory address that is mapped to the device

46
Q

what is a benefit of mmio

A

because its like using ldr and str instructions from the programmers perspective it provides simplicity and convenience for them

47
Q

how does polled io work

A

the cpu monitors a control/status register associated with a port
when a byte arrives at the port a bit in the control register is set
the cpu eventually polls and notices that the “data ready” control bit is set
the cpu resets the control bit, receives the byte and processes it
the cpu resumes polling the register as before

48
Q

how does interrupt driven io work

A

the devices tell the cpu when they have to send data
the cpu proceeds with other tasks until a device requesting service sends an interrupt to it

49
Q
A

digital systems (5 decks)

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