COA Basics (Computer Organization and Architecture) Flashcards
Harvard Architecture
Harvard architecture uses different physical memory for data and instructions, along with separate buses for data and instructions.
Instructions can be executed in a single clock cycle.
Can access instructions and read/write on memory at the same time.
Expensive.
Examples include: 8051, ARM9
Von Neumann Architecture
Von Neumann architecture uses the same physical memory for data and instruction, with the same bus for both data and instruction.
Instruction can be executed in 2 clock cycles.
Cannot access instructions and read/write on the memory at the same time.
Cheap.
Examples include: Pentium Processors, x86
Instruction Execution in a processor is divided into 5 stages
Instruction Fetch (IF)
Instruction Decode (ID)
Operand Fetch (OF)
Execute (EX)
Write Back (WB).
Pipelining
Simultaneous execution of different stages of instruction execution of different instructions.
Pipeline Interlocking/Pipeline Hazard Handling
are measures and handling procedures executed in pipelined processors to deal with errors and discrepancies in a pipeline that can lead to unexpected behavior.
in the process, they minimize the number of pipeline stalls and aid smooth functioning of the pipeline.
Pipelining Interlocking is used for…
hazards that can arise in a pipeline:
1. Structural Hazard: when multiple pipelining stages attempt to access a hardware resource for ex. ALU simultaneously.
2.Data Hazard: read-after-write (RAW) [when one instruction’s read depends on the other instruction’s write, but the write hasn’t been executed yet], write-after-write(WAW) [when two or more instructions attempt to write to he same register simultaneously], write-after-read (WAR) [when one instruction attempts to write to a register that the other instruction is still reading from]
3.Control Hazard: happens during change of control flow of the program, for ex. branch instructions
