Class 25: Computer Systems Flashcards
THe hardware in digital computer system must perform a few basic operations
- Dats storage
- Data movement
- Data transformation
Data movement is done with ____ - Chanel’s for transferring data from one system component to another.
Buses
The system memory bus is divided into an _____ bus, a ____ bus, as well as some ______ (read line, write line, memory read complete line)
Address, data, control lines
The CPU has _____ _______ which it uses for memory accesses
Two reigsters
To put an address on the address bus
MAR (memory address register)
To put data on the data bus or detach data from the data bus
(MDR) memory data register
When the CPU wants to read data from memory, it puts the address of the first byte to be read in in the _____ and sets the read control line to __
MAR, 1
The CPU always reads at least _____ bytes at at time
8
When memory unit detects that the read line is set to 1, it gets address of the bus and gets ____ bytes and that address from memory then puts them on the ____ bus and set the memory read complete control line to ___
8, data, 1
The 8 bytes from the data bus are transferred to _____ when the CPU detects that memory read complete control lines I 1
mdr
When CPU wants to ____ data to memory, it puts the address of first byte to be written to in MAR, puts the data to be written in ___ and sets control line to 1
MAR, MDR
When the memory unit detects that the write control is set to 1, it gets the address off the _____ bus, get the bytes to be written from data bus, and write them to memory at the address it got from the address but
Address
An abstraction that specifies the processor state, format of instructions, the effect of instructions, and PC’s use of x86
Instruction Set Architecture
A quickly accessible location available to a computer’s processor. Consist of a small amount of fast storage
Register
This holds the address of the current instruction. It will be increments to point to the next instruction as par of execution of current instruction
Program counter (PC)
A register where the bits of the instruction are stored so that the instruction can be executed. Before execution, bytes in memory pointed to by the PC will be brought to the ____
Instruction Register (IR)
Combinational logic to implement all arithmetic and logical instructions that CPU performs, execution of these instruction sets some or all of the flags or condition codes.
ALU
A register in the CPU with one-bit flags set by ALU instructions
RFLAGS register
A 64 bit register the CPU uses to put addresses for memory access on the address but
MAR
A 64 bit register which CPU uses to put data on the data bus for write or to retrieve data from the data bus for reads from memory
MDR
Temporary storage for applications which are being executed and data used by applications. Organize as linear array of bytes each with its own unique address starting at 0
Main memory
Two types of memory technology
SRAM and DRAM
Faster acces time than DRAM (faster to read and write)
SRAM
Will lose its information if the supply voltage is removed
Volatile memory
Retain data when powered off
Non volatile memory
Havin smaller faster devices act as a “staging area” for larger slower devices
Caching
Caching works because computer software exhibits _______ ____ _______ in memory access
Property of locality
Refers to the concept of building a memory subsystem which consists of variously level of storage
THe memory hierachry
Storage at higher levels have ____ access time but also has ____ size because more expensive
Faster, smaller
If a particular piece of data (or instruction) is accessed by a program, other data/instructions at nearby locations are more likely to be accessed soon
Spatial locality
If a particular piece of data (or instruction) is acces by a program, the same piece of data/instruction is likely to be access in the near future
Temporal locality
If we speed up one part of the system, the overall effect on system performance depends upon how significant the part sped up is to the overall system and how big that speed improvement was
