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Computer Systems > Circuits > Flashcards

Circuits Flashcards

1
Q

A XOR B

A

OR with an extra curved line, symbol: circle with plus in it
True of only one of A or B is true

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2
Q

XOR in terms of 3 basic gates

A

A XOR B = (A+B) and not(A and B)

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3
Q

What is a functionally complete set of Boolean operators?

A

One which can be used to express all possible truth tables by combining them into a Boolean expression
Examples: AND+OR+NOT, NAND, NOR

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4
Q

Abstraction

A

Hiding details when they aren’t important

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5
Q

Discipline

A

Restricting design choices to make things easier to model, design and combine

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6
Q

What does a circuit have?

A

At least one input terminal, at least one output terminal
Specifies relationship between inputs and outputs
Has a specification of the delay between inputs changing and outputs responding

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7
Q

Combinatorial logic rules

A

Individual gates are combinatorial, all circuit elements are combinatorial, no cyclic paths

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8
Q

Turning a truth table into a sum of products

A

OR together the 1 values
X, Y, Z, F
0, 0, 0, 1
0, 0, 1, 0
0, 1, 0, 0
0, 1, 1, 1
F = (X’ . Y’ . Z’) + (X’ . Y . Z) + …
These are all minterms

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9
Q

Turning a truth table into a product of sums

A

AND together the zero values
X, Y, Z, F
0, 0, 0, 1
0, 0, 1, 0
0, 1, 0, 0
0, 1, 1, 1
F = (X + Y + Z’)(X + Y’ + Z)…
These are all maxterms

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10
Q

Axioms of boolean algebra

A

B = 0 if B != 1, B = 1 if B != 0 (binary field)
not(0) = 1, not(1) = 0
0.0 = 0, 1+1 = 1
1.1 = 1, 0+0 = 0
0.1 = 1.0 = 0, 1+0 = 0+1 = 1

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11
Q

Theorems of one variable

A

B.1 = B, B+0 = B (identity)
B.0 = 0, B+1 = 1 (null element)
B.B = B, B+B=B (idempotency)
not(not(B)) = B (involution)
B.not(B)=0, B+not(B) = 1 (complements)

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12
Q

Associativity

A

(B.C).D = B.(C.D)
(B+C)+D = B+(C+D)

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13
Q

Distributivity

A

B.(C+D) = B.C + B.D
B+(C.D) = (B+C).(B+D)

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14
Q

Covering

A

B.(B+C) = B
B+(B.C) = B

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15
Q

Combining

A

B.C + B.C’ = B
(B+C).(B.C’) = B

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16
Q

Consensus

A

B.C + B’.D + C.D = B.C + B’.D
(B+C).(B’+D).(C+D) = (B+C).(B’+D)

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17
Q

De Morgan’s

A

not(A.B.C.D…) = not(A)+not(B)+not(C)+not(D)+…

not(A+B+C+D+…) = not(A).not(B).not(C).not(D)….

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18
Q

Describe a half-adder

A

Output: Sum = A XOR B
Output: Carry = A AND B
1+1 = 0 with carry
Carry + 0 + 0 = 1
Carry + anything else = results in carry

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19
Q

Describe an adder

A

Made up of two half-adders
Overall input: A, B, Carry in
First adder input: A, B
First adder output: S1, C1
Second adder input: Carry, S1
Output: S2, C1 OR C2

20
Q

What does an n-bit ripple carry adder consist of?

A

Made up of n full-adders
Overall input: b1, a1, C_in = 0
Each adder input: b_n, a_2, carry
Each adder output: S_n, carry
Overall output: S_n, C_out

21
Q

How to create an n-bit subtractor?

A

n-bit adder but set the first carry bit to 1, and negate all the B values

This creates a twos-complement negative

22
Q

How to create an n-bit subtractor?

A

n-bit adder but set the first carry bit to 1, and negate all the B values using NOT gates

This creates a twos-complement negative

23
Q

What is a decoder?

A

Translates a set of n inputs into a set of 2^n outputs, with only one output being 1
Example:
0,0 => 0,0,0,1
0,1 => 0,0,1,0
1,0 => 0,1,0,0
1,1 => 1,0,0,0

24
Q

Mux (multiplexor)

A

A n-bit multiplexor has n+2^n inputs and 1 output
The first n inputs (selector) represent a binary number
The output is the nth bit of the size 2^n part of the input

25
Q

What is a tristate?

A

A buffer that can be disconnected from the bus wire. When disconnected (enable = 0, or 1 for an inverting tristate) the output is weak/”floating”

26
Q

Types of delay in a circuit

A

Contamination delay (t_cd): The minimum delay before the output changes for the first time

Propagation delay (t_pd): The maximum delay before the output is stable

Input changes, output stays at old value for t_cd, starts oscillating, eventually stabilises t_pd after the input changes

27
Q

Causes of delay

A

Capacitance and resistance in a circuit
Speed of light limitation

t_pd and t_cd are different because of different rising and falling delays, multiple inputs and outputs some of which are faster, and because circuits slow down when hot

28
Q

Critical path and short path

A

Critical path: Longest path in the circuit, determines the propagation delay

Short path: Shortest path in the circuit, determines the contamination delay

Delays can be expressed like this: t_pd = 2*t_pd_AND + t_pd_OR

29
Q

Static and dynamic hazards

A

Static hazards: Output undergoes momentary transition when one input changes when it is supposed to remain unchanged. A 1-hazard is where the signal randomly becomes 0 and vice versa.

Dynamic hazards: Output changes multiple times when it’s only supposed to change once

30
Q

Timing diagrams

A

Show the value of a signal as a function of time. The transitions between logic levels are assumed to take place instantaneously.

31
Q

Removing a 1-hazard

A

Draw a Karnaugh map of the output concerned. The 1-hazard occurs where two adjacent 1s are not covered by the same circle. Add another term which overlaps them to the circuit.

32
Q

Removing a 0-hazard

A

Draw a Karnaugh map of the output concerned. The 1-hazard occurs where two adjacent 1s are not covered by the same circle. Identify another term which overlaps them and then add the complement of that term to the circuit.

33
Q

Turning a sum of products into a product of sums

A

F = sum of products
!F = !(sum of products) = product of products = product of sums
Expand this product of sums and simplify to get a sum of products again
now !F = sum of products
F = !(sum of products) = product of products = product of sums

Unwanted terms in a sum of products can be removed by multiplying them by (X + !X)

34
Q

What is a sequential circuit?

A

Output depends on history as well as current input. Fundamental components include latches and flip-flops

35
Q

SR-latch

A

Truth table (SR NOR):
S, R, Q, Q’
0, 0, Q_prev, Q’_prev
0, 1, 0, 1
1, 0, 1, 0
1, 1, 0, 0 (illegal)

Both inputs usually set to 0
If the input S (set) has a pulse of 1, the output becomes 1 and remains 1 even when the pulse is over
If the input R (reset) has a pulse of 1, the output becomes 0 and remains 0 even when the pulse is over

SR NAND has SR NOR’s truth table in reverse

36
Q

D-latch

A

Inputs: D, CLK
The latch value changes to D when CLK is 1

37
Q

D flip-flop

A

The output/stored value changes only at the moment the clock goes high.
The D flip-flop sets the latch value (Q) to D on the rising edge of the clock and remembers its state at all other times

Registers are a bank of flip-flops all driven by the same clock

38
Q

Enabled flip-flop

A

Incorporates an additional input (enable) to control whether the data is loaded into the flip-flop or not
Uses a multiplexor
Either controls the input or the clock (gated clock)
Gated clocks can cause timing errors and glitches

39
Q

What are race conditions?

A

When the behaviour of a circuit depends on which route carries the signal the fastest

40
Q

How do we avoid cyclic paths?

A

Insert registers into them, the registers contain the state of the circuit and only update on a clock edge (synchronised to the clock). If the clock is sufficiently slow, race conditions cannot arise.

41
Q

Formal definition of a synchronous sequential circuit

A

It consists of interconnected elements such that:
- Every circuit element is either a combinatorial circuit or a register
- At least one circuit element is a register
- All registers receive the same clock signal
- Every cyclic path contains at least one register

It has:
- A discrete set of states S0 to S_k-1
- A clock input, whose rising edge indicates when a state change occurs
- A functional specification which details the next state and all outputs for each possible state and set of inputs

42
Q

Timing of a synchronous sequential circuit

A

t_setup = time before rising edge during which inputs must be stable
t_hold = time after rising edge during which inputs must be stable
t_ccq = time until output starts to change
t_pcq = time by which output has stabilised

The time between ticks (T_c) must be at least t_pcq + t_pd + t_setup (time for R1 to stabilise + propagation delay of circuit + time needed for R2 to stabilise)

43
Q

Sequencing overhead

A

t_pd < T_c - (t_pcq + t_setup)
(t_pcq + t_setup) is the sequencing overhead
T_c and the sequencing overhead are fixed and the designer must get all elements of combinatorial logic to work within the bound on t_pd

44
Q

Minimum delay requirement

A

t_cd > t_hold - t_ccq
We add buffers to fix the hold time violation

45
Q

Latency and throughput

A

Latency = time it takes for a single block of data to get from the beginning to the end
Throughput = Rate at which we get data through
T_c = T_c of the longest block
Throughput = 1/T_c

Computer Systems (6 decks)

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