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Computer Systems > Architectures > Flashcards

Architectures Flashcards

1
Q

Difference between von Neumann architecture and Harvard architecture?

A

Harvard has two separate memory spaces for programs and data, and therefore two separate buses
vN only has one memory space for both, with only one bus (this is the litmus test for vN)

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2
Q

What are accumulators?

A

General purpose registers for holding data, interim and final results of calculations, holding data ready to be transferred between I/O and main memory or between different memory locations

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3
Q

What is the Program Counter?

A

Holds the address of the next instruction to be executed

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4
Q

What is the Instruction Register?

A

Holds the actual instruction being executed

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5
Q

What are flags?

A

1 bit registers used to keep track of special conditions, such as:arithmetic carry, overflow, power failure, internal computer error
They are grouped together in one or more Status Registers

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6
Q

What is the Memory Address Register?

A

Register that holds the address of a memory location to be accessed, connected to the memory with a one-way bus

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7
Q

What is the Memory Buffer/Data Register?

A

Register that holds the data being stored in/retrieved from memory location specified in the MAR, connected to the memory with a two-way bus

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8
Q

What is a bus?

A

A physical connection (group of electrical conductors) from one part of the system to another, used for transferring data. They are used to transfer data inside the CPU, between CPU and RAM, and between CPU and components

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9
Q

What are the four categories of buses?

A

Data, Address, Control, Power
Point-to-point buses carry the signal from a specific source to a specific destination
Broadcast buses carry the signal from a specific source to multiple destinations

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10
Q

Three types of MIPS instructions

A

R-type: register operands
I-type: immediate operand
J-type: for jumping

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11
Q

R-type instruction format

A

Human format: Opcode, Dest, Source1, Source2, ShiftAmount, Function

e.g. add, $s0, $s1, $s2

Internal format: Opcode, Source1, Source2, Dest, ShiftAmount, Function
6, 5, 5, 5, 5, 6

e.g. 0, 17, 18, 16, 0, 32

opcode is always 0 for R-type instructions
add, sub, etc. are different functions for R-type

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12
Q

I-type instruction format

A

Human format: Opcode, Dest, Source, Argument

Example: addi $s0, $s1, 5

Internal format: Opcode, Source, Dest, Argument
6, 5, 5, 16

Example: 8, 17, 16, 5

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13
Q

J-type instruction format

A

Opcode, Address
6, 26
Jumps to the address specified in the 26-bit address operand

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14
Q

What are the four parts of the 4GB MIPS address space?

A

Text, global data, dynamic data, reserved

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15
Q

Text segment

A

Stores the program in memory, maximum capacity 256 MB, first four significant bits of any address in this area are 0000

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16
Q

Global data segment

A

Stores global variables, capacity of 64 KB
Global variables are accessed using the pointer $gp

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17
Q

Dynamic data segment

A

The dynamic data segment stores datat hat are dynamically allocated and deallocated throughout the execution of the program.
Data in this segment are stored in a stack and a heap.

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18
Q

Register only addressing

A

Uses registers for all source and destination operands
R-type instructions use Register Only adddressing

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19
Q

Immediate addressing

A

Uses registers and a 16-bit immediate
Some of the I-type instructions use this

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20
Q

Base addressing

A

The base address in the register rs is added to the contents of the immediate

Used in memory access instructions (subset of I-type instructions)

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21
Q

Memory access instructions

A

lw destRegister offset source = load word
lb = load byte
sw sourceRegsiter offset dest = store word
sb = store byte
word = 32 bits = 4 bytes
Example: sw $s3, 4($0) means write $s3 to Word 1

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22
Q

PC-relative addressing

A

0x40 loop: __________
…
0x54 bne $t1, $0, loop
0x58 _____________
…

bne is an I-type instruction. To calculate the imm, subtract the target address from the PC value immediately after the branching instruction and divide by 4. (0x58 - 0x40)/4 = -6
Therefore imm = -6 = 1111 1111 1111 1010

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23
Q

Pseudo-direct addressing

A

This is used to calculate the new value of the Program Counter from a J-type instruction
2 least significant bits and 4 most significant bits are left to 0
j 0x004000A0 = j 0000 0000 0100 0000 0000 0000 1010 0000 = j 0000 0100 0000 0000 0000 1010 00

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24
Q

Call and return in MIPS

A

0x00400200 main: jal simple
0x00400204 …
…
0x00401020 simple: jr $ra

“jal simple” jumps to “simple” like j would do, but also stores in $ra where the program should return after executing “simple”

“jr $ra” jumps to the address stored in $ra
This is R-type, not J-type

25
Q

Arguments and return value in MIPS

A

The caller places arguments into registers $a0 to $a3
Makes a call using jal
The return value is placed in registers $v0 or $v1

26
Q

Input in MIPS

A

li $v0, 5 # load 5 into $v0
syscall # make system call with code 5
move $t0, $v0 # move result (in $v0) to $t0

27
Q

syscall services

A

$v0 = 1, print integer $a0
$v0 = 4, print string $a0
$v0 = 5, read integer and store in $v0
$v0 = 10, exit

28
Q

Process of translating and starting a program

A

The compiler translates high-level code into assembly
The assembler turns assembly code into machine language code (object file)
The linker combines the object file with other machine language code (e.g. from already compiled and assembled libraries)
The loader puts the executable in memory

29
Q

Assembler process

A

The assembler makes two passes through the assembly code. First it assigns instruction addresses and puts all symbols in a table. Then it generates the object file.

30
Q

Microcontrollers and microprocessors

A

Microcontrollers are integrated devices (computers on a chip), and consist of:

  • A microprocessor
  • Memory
  • I/O

They are used in embedded systems (special purpose computer systems designed to perform dedicated functions)
Programs are usually stored in flash memory, often forever

31
Q

AVR registers

A

32 general purpose 8-bit registers as part of the ALU (R0-R31)
The six 8-bit registers R26-R31 should be treated as three 16-bit registers used for addressing

32
Q

AVR memory

A

Data memory = SRAM
Program memory = Flash
Data storage = EEPROM

33
Q

AVR flash memory

A

Divided into two sections: Boot Loader Section and Application Program Section
Program Counter is 14 bits wide, AVR instructions are 16 or 32 bits wide

34
Q

AVR EEPROM

A

1KB of EPPROM, organised as a separate space for storing data
Organised into pages consisting of 4 bytes

35
Q

AVR SRAM

A

Divided into three sections:

Mapping space of ALU registers
I/O registers and extended I/O registers
Internal SRAM

36
Q

AVR types of addressing

A

Direct addressing reaches the entire data space

Registers X, Y and Z (R26 to R31) are the indirect addressing pointer registers

Indirect with displacement mode reaches 63 address locations from the address in the pointer register

In register indirect addressing mode with pre-decrement or post-increment, the address registers X, Y, and Z are decremented or incremented

37
Q

AVR single register addressing

A

Opcode Operand1 (11, 5)
Operand1 is contained in register d (0 <= d <= 31)

Example: NEG R7

38
Q

AVR two register addressing

A

Opcode Operand1 Operand2 (6, 5, 5)

Result stored in Operand2

Example: ADD R3, R4 (R3 := R3 + R4)

39
Q

AVR direct data addressing

A

Instructions are two words long (32 bits), meaning the program counter will be incremented by two

Operand DestOrSourceReg DataAddress

0 <= DataAddress <= 65535

Example: LDS, R3, 2000 (loads a byte from data address $2000 to register $r3)

40
Q

Indirect addressing

A

The operand address is the contents of the X, Y, or Z register

Pre-decrement: X, Y, Z register decremented before the operation

Post-increment: X, Y, Z register incremented after the operation

41
Q

Indirect addressing with displacement

A

Operand address is the result of the contents of the Y or Z register, added to the address contained in six bits of the instruction word (q)
Rd/Rr specifies the destination or source register

42
Q

Example of indirect addressing

A

LD loads one byte from the address in the Y or Z register, LDD does the same but with displacement.

LD Rd, Z [Rd <= (Z)]
LD Rd, Z+ [Rd <= (Z), Z <= Z+1]
LD Rd, -Z [Z <= Z-1, Rd <= (Z)]
LDD Rd, Z+q [Rd <= Z+q]

43
Q

Direct program memory

A

Program execution continues at the address immediate in the instruction words

Example: JMP <label>
<label> is the label of the instruction at address k
PC <= k (0 <= k <= 4,000,000)</label></label>

44
Q

Relative program memory

A

Program execution continues at address PC+k+1 (-2048 <= k <= 2047)

Example:
RJMP <label>
PC <= PC + k + 1</label>

45
Q

Directives

A

.equ assigns a value to a constant
Example: .equ delayVal, 10000

.global deeclares a function as global
Example: .global start

46
Q

SBI instruction

A

Sets bit in I/O register to 1
Syntax: SBI A,b (0 <= A <= 31, 0 <= b <= 7)
CBI does the same thing except it sets the bit to 0

47
Q

Status register

A

An 8-bit register part of the CPU. Its bits are used as flags.

48
Q

Reading values from the input pin

A

btnLED:
SBIC PIND, 2
RJMP blink
RJMP btnLED

The status of the input pin is stored in a bit named (PIND,2)
The bit DDRD,2 controls whether D02 is used as an input or output pin
The SBIC instruction checks if a bit in an I/O register is 0, and skips an instruction if it is

49
Q

Controlling the output pin

A

SBI DDRB,4 sets pin D12 as the output pin (bit 4 in the I/O register <= 1)
Its behaviour is now controlled PORTB,4

When PORTB,4 is 1, the LED is on

50
Q

SUBI instruction in AVR

A

SUBI Rd, x (Rd -= x)
If the result of the subtraction is zero, the value in the Z bit of the status register will be 1

51
Q

Conditional branching in AVR

A

BRNE label: branches to label if Z is equal to 1

52
Q

CISC architecture

A

Complex Instruction Set Computers:
Large number of specialised instructions
Wide variety of addressing modes
Instruction length varies
Comparatively few general purpose registers

Examples: IBM mainframe, x86

53
Q

RISC architecture

A

Reduced Instruction Set Computers (RISC)
Limited and simplified instruction set, but very efficient
Register-oriented instructions with limited memory access
Fixed length and format of instructions
Limited addressing modes
Large bank of registers

54
Q

CISC vs RISC comparison

A

RISC used to be faster but produce bigger programs
Nowadays RISC and CISC have become more similar, and have similar performance

55
Q

Key things to consider when approaching a new architecture

A

Data word length
Registers
How memory is organised
Instructions

56
Q

Pipelining

A

Separate execution units for different types of instruction to allow parallel execution of unrelated instructions

57
Q

Branch problem solutions

A

When we reach a branch statement we don’t know what the next instruction will be

Solutions: Work on both outcomes until the branch is resolved, predict the branch outcome based on previous visits or programmer hint, requiring the following instruction to not be dependent on the branch, analyse upcoming instructions and do the ones that do not depend on the current pipeline first

58
Q

Superscalar processing

A

Specialist units for different types of instruction, several for the most common instructions
Each unit has a pipeline, if they’re all filled then the overall processor can execute more than one instruction per clock cycle

59
Q

Superscalar processing complications

A

Conflicts for CPU resources, dependencies on prior results may be lost, instructions may complete in the wrong order, branch problems

Computer Systems (6 decks)

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