Chapter 9 test Flashcards
A physical memory cache is designed to search the local cache or access the underlying memory, but not in parallel.
False
A reference to a missing page is called a page fault.
T
A virtual address space can be contiguous.
T
After separating read and write operations, there is no need for additional measurement.
???
Although a variety of caching mechanisms exist, they share 4 general characteristics. Name two of the four characteristics.
Small, Active, Transparent, Automatic
An alternate to segmentation that has been very successful is known as demand padding.
T
An architect views a memory as a solid-state digital device that provides storage for data values.
T
An MMU creates a real address for the processor.
F
Any measure of memory performance must give two values. What operations do those values represent?
Read operations and wrote operations.
Byte addressing is convenient for programming because it gives a programmer an easy way to access small data items.
T
Cache designers use the term hit miss ration to refer to the percentage of requests in the sequence that are not satisfied from the cache.
???
Caching can be used with hardware and software.
T
Caching cannot be used with non-textual data.
F
Caching has 4 general characteristics: it is large, static, visible, and not automatic.
F
Caching reduces the Von Neumann bottleneck
T
Computers that use DRAM contain an extra hardware circuit called static circuit.
F
Conceptually, SRAM stores each data bit in a miniature digital circuit composed of multiple transistors similar to the flip-flop.
T
Correct terminology when speaking about page frames is that software loads a page into memory of frame.
T
Currently, the distinction between L1 and L2 cache is fading.
T
Data items in a cache are not limited to a specific type, form, or size.
T
Density and latency stand out when referring to access memory technology.
T
Despite the cost and power consumption advantages of DRAM most computer memory is composed of SRAM rather than DRAM.
F
Dividing a virtual address space on a boundary that corresponds to a power of two allows the MMU to perform address translations without requiring arithmetic operations.
T
Early computer designers thought that multi-programming was impractical.
T
Engineers use this term to denote the type of memory used as the primary memory system in most computers.
Random access memory.
For virtual memory schemes, no single scheme is optimal in all cases.
T
Given a parallel connection between a processor and memory, a connection that contains N wires, allows 2^N bits of data to be transferred simultaneously.
F
How do architects view memory?
A solid-state digital device that provides storage for data values.
How is physcial memory organized?
It is organized into words.
In essence, a DRAM chip is a perfect memory device.
F
In order for a cache to resolve the ambiguity that occurs because multiple applications use the same range of address two solutions have been created. Name one of th esolutions.
Cache flush operations, A disambiguating identifier.
In paging, the number of bytes per page is chosen to be a power of 8.
F
In physical memory each read and write operation applies to an entire world.
T
In segmentation, each program is divided into fixed-sized blocks called pages.
F
It is not possible for a memory management unit to use two different types of physical memory in a single virtal address space.
F
Many processors use bit addressing because it provides the most convenient interface for programmers.
T
Memory organization refers to two structures. What are the two structures and label them as internal or external?
Internal hardware structure and external addressing structure.
Memory systems use a ___ that controls exactly when a read or write operations begins.
Clock
Memory systems use a clock that controls exactly when a read or write operation begins.
T
MMU cannot use what operation to implement address translation.
Subtraction
Most personal computers use a cache hierarchy. The cache at the top of the hierarchy is usually the smallest and fastest of the cache hierarchy.
T
Most ram is volatile.
T
Name the two different types of RAM technologies.
SRAM and DRAM
Name the two technologies needed for a virtual memory system that supports demand paging.
Hardware that handles address mapping and software that moves pages between.
Name two characteristics of caching mechanisms.
Small and active.
N-Way interleaving describes the theoretical number of underlying memory modules.
F
