Chapter 6, 7

Question 0

K-Maps

Answer 0

karnaugh maps

• graphical methods to help us find opportunities to combine terms
• minterms differing in one variable are adjacent in the map
• can clearly see opportunities to combine terms

Question 1

Delay analysis

Answer 1

The time from inputs changing to new correct stable output.

Question 2

Given a state machine identify equlivent states

Answer 2

Two states are equlivent if:

1) they assign the same values to outputs
2) AND for all possible sequences of inputs the FSM outputs will be the same starting from either state.

Question 3

State Minimization

Answer 3

Partitioning method using state tables
Create partitions (groups) of equivalent states
– states in the same partition maybe equlivent
– states in different partitions are not equivalent
1st test: group outputs
2nd test: for all possible sequence of inputs the FSM outputs will be the same starting from either state

Question 4

NAND Only design process

Answer 4

Recall that cMOS transistors more effectively implement NAND and NOR gates rather then AND and OR gates
The underlying reason is that pMOS transistors conduct 1’s well but not 0’s
Furthermore creating a gate array is easier using just 1 type of gate
NAND is a universal gate because it can implement any Boolean function.

Question 5

CLA

Answer 5

Carry look ahead adder
Motivation:
- if we don’t know the carry in what could we do?
- when would we always generate a carry? g_i=a_i*b_i
- when would we propagate the carry? p_i=a_i + b_i
A four bit CLA adder
Generate a g & p for each bit
Use g & p and carry in to generate all c’s
Also use them to generate block g and p
CLA principle can be used recursively

Question 6

Mealy Machine Design

Answer 6

If function of present state and FSM inputs

Mealy has fewer states but output d does not update for 1 cycle.

Question 7

Moore Machine Design

Answer 7

Regular.