Chapter 3

Question 0

Level Sensitive SR latch

Answer 0

Called level sensitive because the latch is only sensitive to its S & R inputs when the level or the enable is 1.

Question 1

SR Latch

Answer 1

Implements a bit storage building block

Problem with SR Latch is if S & R are both 1 an undefined behavior results

Question 2

D-Latch

Answer 2

So this just means that the click & the set have to be 1 to make Q=1 then click has to = 1 and R = 1 to make Q -> 0
Problem: hard to pick a c that just the right legnth.

Question 3

D-Flip Flop

Answer 3

Bit storage that moves on clock edges not level. It’s two D-latches.

Question 4

FSM Formal Definition

Answer 4

A way to describe desired behavior of a sequential circuit.

Question 5

FSM Design Process

Answer 5

Step 1: capture the function (create a truth table or function)
Step 2A: create equations
Step 2B: implement the functions as a gate based circuit

Question 6

Exclusiveness

Answer 6

Each FSM state can only have 1 place that each output goes,
I.e. State 1 -> State 2 if a==1
State 1 -> State 3 if a==0
That can’t work.

Question 7

Completeness

Answer 7

Each state must have a output for each combination of inputs.
I.e. State 1 -> State 2 if a==0
State 1 -> State 1 if b==0
What if a and b are both 0, what if neither are 0

Question 8

Propagation Delay

Answer 8

t_pcq = time after clock edge that the output Q is gaurenteed to be stable

Question 9

Contamination Delay

Answer 9

t_ccq= time after clock edge that Q might be unstable (ie start changing)

Question 10

Metastability

Answer 10

Violating setup/hold time can lead to bad situation known as Metastability. Metastable state: Amy state other than a 1 or 0