CHAPTER 5: The Processor

Question 1

combinational element

Answer 1

operational element, such as an AND gate or an ALU

Question 2

state element

Answer 2

memory element, such as a register or a memory

Question 3

clock methodology

Answer 3

approach used to determine when data is valid and stable relative to the clock

Question 4

edge-triggered clocking

Answer 4

clocking scheme in which all state changes occur on a clock edge

Question 5

control signal

Answer 5

signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit

Question 6

asserted

Answer 6

signal is logically high or true

Question 7

deasserted

Answer 7

signal is logically low or false

Question 8

datapath element

Answer 8

unit used to operate on or hold data within a processor. In the LEGv8 implementation, the datapath elements include the instruction and data memories, the register file, the ALU, and adders

Question 9

program counter

Answer 9

register containing the address of the instruction in the program being executed

Question 10

register file

Answer 10

state element that consists of a set of registers that can be read and written by supplying a register number to be accessed

Question 11

sign-extend

Answer 11

increase the size of a data item by replicating the high-order sign bit of the original data item in the high-order bits of the larger, destination data item

Question 12

branch target address

Answer 12

address specified in a branch, which becomes the new program counter (PC) if the branch is taken. In the LEGv8 architecture, the branch target is given by the sum of the offset field of the instruction and the address of the branch

Question 13

branch taken

Answer 13

branch where the branch condition is satisfied and the program counter (PC) becomes the branch target. All unconditional branches are taken branches

Question 14

branch not taken (untaken branch)

Answer 14

branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch

Question 15

truth table

Answer 15

a representation of a logical operation by listing all the values of the inputs and then in each case showing what the resulting outputs should be

Question 16

don’t-care term

Answer 16

element of a logical function in which the output does not depend on the values of all the inputs. Don’t-care terms may be specified in different ways

Question 17

opcode

Answer 17

field that denotes the operation and format of an instruction

Question 18

single cycle implementation (single clock cycle implementation)

Answer 18

implementation in which an instruction is executed in one clock cycle. While easy to understand, it is too slow to be practical

Question 19

pipelining

Answer 19

implementation technique in which multiple instructions are overlapped in execution, much like an assembly line

Question 20

structural hazard

Answer 20

planned instruction cannot execute in the proper clock cycle because the hardware does not support the combination of instructions that are set to execute

Question 21

data hazard (pipeline data hazard)

Answer 21

planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available

Question 22

forwarding (bypassing)

Answer 22

method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory

Question 23

load-use data hazard

Answer 23

specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction.

Question 24

pipeline stall (bubble)

Answer 24

stall initiated in order to resolve a hazard

Question 25

control hazard (branch hazard)

Answer 25

proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected

Question 26

branch prediction

Answer 26

method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome

Question 27

latency (pipeline)

Answer 27

the number of stages in a pipeline or the number of stages between two instructions during execution.

Question 28

nop

Answer 28

instruction that does no operation to change state

Question 29

flush

Answer 29

discard instructions in a pipeline, usually due to an unexpected event

Question 30

dynamic branch prediction

Answer 30

prediction of branches at runtime using runtime information

Question 31

branch prediction buffer

Answer 31

small memory that is indexed by the lower portion of the address of the branch instruction and that contains one or more bits indicating whether the branch was recently taken or not

Question 32

branch target buffer

Answer 32

structure that caches the destination PC or destination instruction for a branch. It is usually organized as a cache with tags, making it more costly than a simple prediction buffer.

Question 33

correlating predictor

Answer 33

branch predictor that combines local behavior of a particular branch and global information about the behavior of some recent number of executed branches

Question 34

tournament branch predictor

Answer 34

branch predictor with multiple predictions for each branch and a selection mechanism that chooses which predictor to enable for a given branch

Question 35

vectored interrupt

Answer 35

interrupt for which the address to which control is transferred is determined by the cause of the exception

Question 36

imprecise interrupt (imprecise exception)

Answer 36

Interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception

Question 37

precise interrupt (precise exception)

Answer 37

interrupt or exception that is always associated with the correct instruction in pipelined computers

Question 38

instruction-level parallelism

Answer 38

parallelism among instructions

Question 39

multiple issue

Answer 39

scheme whereby multiple instructions are launched in one clock cycle

Question 40

static multiple issue

Answer 40

approach to implementing a multiple-issue processor where many decisions are made by the compiler before execution

Question 41

dynamic multiple issue

Answer 41

approach to implementing a multiple-issue processor where many decisions are made during execution by the processor

Question 42

issue slots

Answer 42

positions from which instructions could issue in a given clock cycle; by analogy, these correspond to positions at the starting blocks for a sprint

Question 43

speculation

Answer 43

approach whereby the compiler or processor guesses the outcome of an instruction to remove it as a dependence in executing other instructions

Question 44

issue packet

Answer 44

set of instructions that issues together in one clock cycle; the packet may be determined statically by the compiler or dynamically by the processor.

Question 45

very long instruction work (VLIW)

Answer 45

style of instruction set architecture that launches many operations that are defined to be independent in a single wide instruction, typically with many separate opcode fields

Question 46

use latency

Answer 46

number of clock cycles between a load instruction and an instruction that can use the result of the load without stalling the pipeline

Question 47

loop unrolling

Answer 47

technique to get more performance from loops that access arrays, in which multiple copies of the loop body are made and instructions from different iterations are scheduled together

Question 48

register renaming

Answer 48

renaming of registers by the compiler or hardware to remove antidependences

Question 49

antidependence (name dependence)

Answer 49

ordering forced by the reuse of a name, typically a register, rather than by a true dependence that carries a value between two instructions

Question 50

superscalar

Answer 50

advanced pipelining technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution

Question 51

dynamic pipeline scheduling

Answer 51

hardware support for reordering the order of instruction execution to avoid stalls

Question 52

commit unit

Answer 52

unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release the result of an operation to programmer-visible registers and memory

Question 53

reservation station

Answer 53

buffer within a functional unit that holds the operands and the operation

Question 54

reorder buffer

Answer 54

buffer that holds results in a dynamically scheduled processor until it is safe to store the results to memory or a register

Question 55

out-of-order execution

Answer 55

situation in pipelined execution when an instruction blocked from executing does not cause the following instructions to wait

Question 56

in-order commit

Answer 56

commit in which the results of pipelined execution are written to the programmer visible state in the same order that instructions are fetched

Question 57

fallacy: pipelining is easy

Question 58

fallacy: pipelining ideas can be implemented independent of technology