Chapter 4 RAM Flashcards
What is the MCC
Memory controllor chip, optimises the flow of data to and from the CPU, when the CPU needs data from RAM it asks the MCC that then deals with the intracacies of the process and where that data is exactly located on the RAM sticks
How did the processors begin to handle byte sized instruction when DRAM chips were 1 bit wide
8 DRAM chips can be utilised to turn it into a byte connection where the MMC has a byte length address bus to communicate with the CPU, RAM can then transfer 8 bit machine code instructions to the CPU from each DRAM module to formulate a byte.
How would the MMC and CPU handle 2 byte instructions with 1 byte width between them and 1byte of DRAM
They can split the instructions into two seperate bytes and transfer them to the cpu individually this would take double the time to process
To solve the problems of space that arose from the dram chips on motherboards what did manufactures to do combat this issue
they began to install dram modules of larger size on a stick called a module and single inline memoryh module with eight dram chips.
What is SDRAM
It is a form of syncrhonous DRAM that is timed with the system clock just like the CPU and MCC this allows for the MCC to know when the DRAM is raedy for data to grab, this results in very little wasted time.
* first appears on a stick called dual inline memory module
* all these DIMM varieties delivered 64-bit-wide data to match the 64-bit data bus of every CPU since the original Pentium.
How do you take advantage of the SDRAM feature
You must have a computer that would be able to support the features, some forms require two sticks to make a full bank as each stick provides only half the bus width
As SDRAM matches the system clock, so its clock speed matched the front side bus what are the five common clock speeds
66, 75, 83 ,100 and 133
* the RAM speed had to martch or exceed the systems speed or the computer would be unstable and wouldnt work at all, the speeds were suffixed with PC
DDR3 RAM comparison to previous generation and its benefits
- higher speeds, more efficient architecture
- 30% lower power consumption
- 240 pinn DIMM like predecessor, but slotted differently
- SODIMMS have 204 pins
- some had XMP
- higher density memory chips
What is XMP and AMDS version
enables power users to overclock their RAM easily, boosting already fast memory
AMD released their version called AMP AMD Memory Profile
What is meant by the dual channel memory architecture
This is when the Memory controller chip is able to access the RAM modules or sticks simulataneously i.e. if there is access to three stick it will only be able to access 2 at a given time
What is tripple channel memory archeticture
some DDR3 modules supported triple channel memory architecture or quad this was similar to dual channel memory but with three or four sticks of RAM.
What are the conditions for multiple channel memory architecture
- DIMM config must be the same across RAM modules -memory sizem number of chips etc however this can be overided, if there are two modules that arent the same the motherboard will cause the faster RAM module to match the speeds of the slower one however this does introduce a form of instability into the system.
