Chapter 3 CPU Flashcards
How does the CPU utilise the external data bus
by creating on and off patterns with the bits that have a standardised code between the CPU and EBD, data can be transferred from and to the CPU.
Registers within the CPU are required to perform math problems
4 rows of 16 bit registers are within the CPU that store internal commands and data.
Registers provide the man in the box with a workplace for problems.
what are the four most common general purpose registers in an intel machine
- AX
- BX
- CX
- DX
What are the three considerations when designing a CPU
- Industry standard architecture for the CPU. instruction set for how the CPU will handle code and interact with other components
- chip floorplan for how the transistors and other parts of the CPU interconnect
- fabrication company puts all the designs into action and creates the physical CPU
What three main companies are responsible for most CPU development today
- Intel - produces own chip and fabrication
- Advanced RISC Machine ARM - licences processors to other companies like apple Samsung who design the chips and use fabrication companies to design the processors
- Advanced Micro Devices AMD - fabless semiconductor company that relies on another company to produce its processors
Where are ARM processors usually located?
- They are often found in SoC system on a chip.
what is microarchitecture
it is the foundation used for the inner workings of a CPU, adjustments are made by the company every few years while keeping the CPU in the same name series.
* This could drastically increase performance.
what is the key considerations a company takes when creating a mobile processor
- must use as little electricity as possible and give off as little heat.
- engages in thermal throttling as the heat dissipation on a mobile device is relatively smaller.
- intel and and have good engineers that can facilitate for this and often have done so
Clock multiplier purpose and functionality
all processors run at some multiples of the system clock speed so increasing the clock multiplier if the bus speed is 100 Mhz and multiplier is x32 it would result in 3.2Ghz core speed
64 bit processing
the EDB has gradually been expanded over decades going from 8 to 16 to 32 to 64 and address bus staying at 32 as its size being so large means such a large amount of ram is required 16 EB of RAM
x86 CPUs
CPUs from the early days can be placed here as they used the earliest intel cpu architecture and developed upon that instruction set
x64 CPUs
marketing folks required to distinguish there softwares as some wasn’t compatible with the new chipset versions and this created a mess
x86-64 processors
earlier 32 bit processors were marked as x86 and the 64 bit processors could handle their code and are by definition x86 processors too hence 64 bit processors were also determined as x86-64
virtualisation support meaning
running more than one operating system at a time
* benefits of the cpu having that function saved programmers lots of time instead of individually allocation slots of memory and data to each os
parallel execution
process multiple commands and instructions parallel to one another or simultaneously
to receive a command from the data bus do the calculation and send the data back to the data bus what process is required
fetch
decode
execute
write
difference in old vs modern processors with handling FDEW cycle
old processors treated each stage did its job and in every clock cycle three of the four circuits sat idle. today the circuits are in a conveyer belt fashion known as pipelining multiple circuits are performing multiple jobs.
what are some problems with pipelining
due to the conveyer belt nature of the process if a complex calculation was to arise this would force the pipeline to stop the cpu tries to avoid these pipeline stalls
what stage often causes the most pipeline stalls
the decode stage, current processors use multiple decode stages to reduce the chance of pipeline stalls due to complex decoding
purpose of the arithmetic logic unit
handles the integer math calculations within the CPU
How do processors deal with floating point math
They posses a floating point unit, sometimes there was only access to one ALU or FPU at a time and the FPU would often take many stages to execute the complex commands
thread
series of instructions designed to do a particular job with the data, most instructions aren’t processed sequentially and are often reused
SRAM
static ram Designed to reduce the wait states of data transfer between CPU and RAM, preloads as many instructions as possible and keeps copies of already run instructions and data in case the cpu utilises them soon. this is utilised in a fashion called cache
