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FPGA (FINAL) > Chapter 3: Signal and Data Type > Flashcards

Chapter 3: Signal and Data Type Flashcards

1
Q

What is the function and purpose of local signals?

A

Connect components within an architecture

In order to form a larger system.

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2
Q

What is the function of port signals?

A

Provide a system’s interface to its environment.

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3
Q

What are the object Class?

4

A
  1. Signal.
  2. Constant.
  3. Variable.
  4. File.
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4
Q

What is signal?

A
  • An object with a current value and future values.

- The future values can be changed, as many times as desired, using signal assignment statements.

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5
Q

What is constant?

A

An object whose value cannot be changed after it is initially specified.

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6
Q

What is variable?

A
  • An object with only a current value.

- A variable’s value can be changed, as many times as desired, using variable assignment statements.

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7
Q

What is file?

A

An object that consists of a sequence of values of a specified type.

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8
Q

What are synthesizable among the object class?

A
  1. Signals.
  2. Constants.
  3. Variables.
    And they are used in design description.
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9
Q

What is not synthesizable among the object class?

A
  1. Files.

And it is mostly used in testbenches.

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10
Q

What are the objects types?

A
  1. Scalar type.
  2. Composite type.
  3. Access type.
  4. File type.
  5. Protected type.
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11
Q

What is scalar type?

A

Has a single indivisible value, which can be either numeric or enumerated.

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12
Q

What is composite type?

A
  • Consists of a collection of elements each with a value.
  • There are two kinds of composite types:
    (a) arrays and
    (b) records.
  • All elements in an array are of the same type.
  • Elements in a record can be of different types.
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13
Q

What is access type?

A

Provides access to objects of a given type, similar to a pointer in conventional programming languages.

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14
Q

What is file type?

A
  • Provides access to objects containing a sequence of values of a given type (such as disk files).
  • The value of a file type is the sequence of values contained in the host system file.
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15
Q

What is protected type?

A

Provides atomic and exclusive access to variables accessible to multiple processes (global variables).

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16
Q

Which object types are synthesizable?

A
  1. Scalar type.

2. Composite type.

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17
Q

How many types are there in scalar types? List them.

A

Four:

  1. Enumeration types. (discrete)
  2. Integer types. (discrete and numeric)
  3. Physical types. (numeric)
  4. Floating types. (numeric)
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18
Q

What are the enumeration types?

A
  1. bit.
  2. boolean.
  3. character.
  4. severity_level.
  5. file_open_kind.
  6. file_open_status.
    All of them are predefined.
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19
Q

What is the integer type?

A
  1. integer.
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20
Q

What is the physical type?

A
  1. time.
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21
Q

What are the floating type?

A
  1. real.
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22
Q

Scalar Types Tree:

A

Refer to files with the name final.

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23
Q

How an enumeration type is declared?

A
  • By simply listing all possible values for the type.

- Must be at least one value in the list.

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24
Q

What are the bit values?

A

0, 1

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25
Q

What are boolean values?

A

True, Flase

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26
Q

What are integer values?

A

-(231) to +(231-1)

27
Q

What are the natural values?

A

Positive values including 0

28
Q

What are the positive values?

A

Positive values excluding 0

29
Q

What are the character values?

A

ASCII characters (eg. ‘A’)

30
Q

What are the time values?

A

values include units (eg. 10ns, 20us)

31
Q

What is a subtype?

A

A type derived from another type.

32
Q

What is a base type?

A

The type from which the subtype is derived.

33
Q

Does the subtype follows the type of its base type?

A

Yes.

34
Q

What is the STD_LOGIC_1164 package defines?

A

Defines a nine value logic system.

35
Q

What is defined in this package?

A
  1. Type std_ulogic and
  2. its subtype std_logic. (Both are enumerated types)
  3. Operators
  4. Function of operands of these types.
36
Q

How many driving strength are there that are represented by std_ulogic? List them,

A

Three:

  1. forcing.
  2. weak.
  3. high impedance.
37
Q

What are the type std_ulogic is declared in package STD_LOGIC_1164 as?

A 
type std_ulogic is(
  'U' -- Uninitialized
  'X' -- Forcing Unknown
  '0' -- Forcing Low
  '1' -- Forcing High
  'Z' -- High Impedance
  'W' -- Weak Unknown
  'L' -- Weak Low
  'H' -- Weak High
  '-' -- Don't Care);
38
Q 
State the Strength properties of:
U
X
0
1
Z
W
L
H
-
A 
none
forcing
forcing
forcing
high impedance
weak
weak
weak
none
39
Q

What is the type of type std_ulogic?

A
  • Unresolved type.

- U in ulogic is unresolved.

40
Q

What is a resolve type?

A
  • A type declared with a resolution function.
41
Q

How does a std_logic is declared in package STD_LOGIC_1164?

A

subtype std_logic is resolved std_ulogic;

42
Q

What is the disadvantage of using std_logic instead of std_ulogic?

A

Signals that are unintentionally multiply driven will not be detected as an error during compilation.

43
Q

What does IEEE standard 1164 recommends?

A

To use std_logic instead of std_ulogic even if a signal has only a single source.

44
Q

What does composite types consist of?

A
  • A collection related elements that form either an array or a record.
  • Each element has a value.
45
Q

What are the possible elements that are contained in the composite types?

A
  1. Scalar.
  2. Composite.
  3. Access type.
46
Q

How many types of composite types are there? List them.

A

Two:

  1. Array types.
  2. Composite types.
47
Q

How many array types are there? List them.

A

Two:

  1. Unconstrained array types.
  2. Constrained array types.
48
Q

What are the predefined unconstrained array types?

A
  1. bit_vector

2. string

49
Q

What are the predefined VHDL aggregate data types?

A
  1. bit_vector array (natural range <>) of bit.
  2. string array (natural range <>) of char.
  3. text file of “string”.
50
Q

What is the function of an array type?

A

Group elements of the same type together as a single object.

51
Q

What does a one dimensional array is also called?

A

A vector.

52
Q

What is an unconstrained (unbounded) array?

A

An array whose dimensions and indices types are specified when the array type is declared, but the bounds for each dimensions are left unspecified.

53
Q

What is the purpose of unconstrained array?

A
  • Allows multiple subtypes to share a common base type.

- Allow subprogram to be written to handle arrays of any length.

54
Q

What is a type bit_vector?

A

Is a predefined one-dimensional unconstrained array of elements of type bit.

55
Q

What is a type std_logic_vector?

A

Is a one-dimensional unconstrained array of elements of type std_logic.

56
Q

Which package does bit_vector is defined?

A

STANDARD

57
Q

Which package does std_logic_vector is defined?

A

STD_LOGIC_1164

58
Q

What are the IEEE Standard 1164 aggregate data types?

A
  1. std_ulogic_vector array (natural range <>) of std_ulogic.

2. std_logic_vector array (natural range <>) of std_logic.

59
Q

Examples of writing std_ulogic_vector and bit_vector:

A
  • signal dbus: bit_vector(15 downto 0);
  • dbus (7 downto 4) <= “0000”; (4-bit slice of dbus)
  • signal cnt: std_ulogic_vector(1 to 3);
  • variable message: string(0 to 20);
60
Q

Which one is the type and the range in integer type declaration?

(i) type ten is range 0 to 9;
(ii) type digit is range 0 to 9;

A

(i) type - ten
range - 0 to 9
(ii) type - digit
range - 0 to 9

61
Q

type integer is range implementation_defined;

subtype tenn is range 0 to 9;
subtype digitt is range 0 to 9;

signal x, y: tenn;
signal f, g: digitt;

can we assign:

(i) x <= y;
(ii) x <= g;

A

(i) Yes, because these signals are the same type.
(ii) Yes, because the base type of these subtypes are the same type, which is integer.

For subtype, need to look at its base type to determine its type.

62
Q

Type translation made by a synthesizer:

(i) bit
(ii) bit_vector
(iii) boolean
(iv) integer
(v) enumeration
(vi) record
(vii) 2-D array

A

(i) std_logic
(ii) std_logic_vector
(iii) std_logic
(iv) std_logic_vector
(v) std_logic_vector
(vi) (record elements are split)
(vii) (array elements are split)

63
Q

Operators:

A

Refer to files with the name final.

FPGA (FINAL) (4 decks)

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