Chapter 1: Introduction to FPGA (PLDs and FPGAs)

Question 1

What is FPGA stands for?

Answer 1

Field Programmable Gate Array

Question 2

What is FPGA?

Answer 2

Programmable semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects.

Question 3

What does early programmable logic device (PLD) offers?

Answer 3

Early PLD offers programmable arrays to implement 2-level logic in sum-of-product (SOP) form.

Question 4

Hierarchy of PLD

Answer 4

Refer to pic in Final FPGA folder.

Question 5

FPGA HISTORY - PLDs (PROMs) (5)

Answer 5

1. Pre-wired AND array & programmable OR array.
2. PROMs were originally intended for use as a computer memories to store programs and constant data.
3. However, engineers used them to implement lookup tables and state machines.
4. PROMs can be used to implement any block of combinational logic.
5. Important limitation of PROM: the AND plane produces all products whether they are used or not, which limits the number of inputs.

Question 6

What is the important limitation of PROM?

Answer 6

The AND plane produces all products whether they are used or not, which limits the number of inputs.

Question 7

How many inputs does AND and OR have in PROM?

Answer 7

AND: 3 inputs.
OR: 8 inputs.

Question 8

PLD (PROM) diagram:

Answer 8

Refer to pic in Final FPGA folder.

Question 9

What can programmable links in the OR array can be implemented as?

Answer 9

Programmable links in the array can be implemented as fusible links or as EPROM/EEPORM transistors.

Question 10

How many types of PLDs are there? State the types.

Answer 10

[Not so sure] 
<>
Four:            or          Two:
1. PROM                     1. SPLDs
2. PLA                        2. CPLDs
3. PAL
4. CPLD

Question 11

FPGA HISTORY - PLDs (PLAs) (5)

Answer 11

1. Programmable Logic Arrays (PLAs) allowed both the AND and OR plane to be programmed.
2. Number of AND functions in the AND array is independent of the number of inputs to the device.
3. Product terms can be shared among output functions.
4. The programmable links slow signals, thus PLAs are slower then PROMs.
5. PLAs never achieved any significant level of market presence.

Question 12

PLD (PLAs) diagram:

Answer 12

Refer to pic in Final FPGA folder.

Question 13

FPGA HISTORY - PLDs (PALs) (4)

Answer 13

1. Programmable Array Logic (PALs) were introduced in late 70’s to address speed problem of PLAs.
2. The AND array is programmable and the OR array is predefined, therefore they are faster than PLAs.
3. However, PALs only allow a restricted number of product terms to be OR’ed, at least on chip.
4. Real devices have many more inputs and outputs plus a variety of options available including:
   (a) The ability to invert the outputs
   (b) The ability to tristate the outputs
   (c) The ability to latch the outputs
   (d) The ability to configure certain pins as input or output

Question 14

PLD (PALs) diagram:

Answer 14

Refer to pic in Final FPGA folder.

Question 15

FPGA HISTORY - CPLD (6)

Answer 15

1. In ‘84, Altera introduced a CPLD based on a combination of CMOS and EPROM technologies.
2. CMOS allowed low power and high density, while EPROM enabled these devices to be used for development and prototyping.
3. Altera’s real contribution was to use an interconnection array with less than 100% connectivity.
4. This will result in increasing the complexity of software but keep the device scalable in terms of speed, power and cost.
5. Interconnection matrix usually has more wires than the individual SPLD blocks
   - –> a MUX is used to connect them.
6. The programmable switches may be EPROM, EEPROM, FLASH or SRAM based.

Question 16

What is Altera’s real contribution?

Answer 16

To use an interconnection array with less than 100% connectivity.

Question 17

CPLD diagram:

Answer 17

Refer to pic in Final FPGA folder.

Question 18

What does a generic CPLD structure typically consist of?

Answer 18

A generic CPLD structure typically consists of several SPLD blocks sharing a common programmable interconnection matrix.

Question 19

SPLDs and interconnect of CPLD:

Answer 19

Both SPLD and interconnect can be programmed.

Question 20

FPGA HISTORY - Early FPGAs (6)

Answer 20

1. In the early ’80s, a gap emerged in the digital IC continuum.
2. At one end, SPLDs and CPLDs provided high (i) configurability, (ii) fast design, and (iii) modification times,
   but supported only small to moderate functions.
3. At the other end, ASICs supported large complex designs but were immutable once fabricated, expensive, and time-consuming to design.
4. The first FPGAs were based on CMOS and used SRAM cells for configuration.
5. The early chips used an array of programmable logic blocks (PLBs), which comprised:
   (i) a 3-input lookup table (LUT),
   (ii) a register, and
   (iii) a MUX.
6. Each PLB can be programmed individually to perform a unique function.

Question 21

Gap between PLDs and Arrays.

Answer 21

Refer to pic in Final FPGA folder.

Question 22

Who developed FPGA?

Answer 22

Xilinx

Question 23

When was FPGA built?

Answer 23

in ‘84

Question 24

Why do Xilinx created FPGA?

Answer 24

to fill the gap between PLDs and ASICs.

Question 25

The gap between PLDs and ASICs:

Answer 25

Refer to pic in Final FPGA folder.

Question 26

What’s the function of an LUT?

Answer 26

Can implement any 3-input logic function.

Question 27

What is the function of a MUX?

Answer 27

Allows selection of the LUT output or an external input.

Question 28

Registers (FF) can be triggered by?

Answer 28

Can be triggered by a positive or negative-going clock

Question 29

PLB diagram:

Answer 29

Refer to pic in Final FPGA folder.

Question 30

Early FPGA architecture:

Answer 30

Refer to pic in Final FPGA folder.

Question 31

How many types of FPGA are there? State the types.

Answer 31

Three:

1. Anti-fused-based.
2. EPROM-based.
3. SRAM-based.

Question 32

FPGA Technologies - Anti-fused-based (5)

Answer 32

1. Anti-fused-based FPGA are programmed off-line using a special chip programmer.
2. Advantages:
   (a) Configuration is retained during power cycle (non-volatile).
   (b) They don’t require an external memory to store their configuration data, which saves on board cost and real estate.
3. Disadvantages:
   (a) One-time-programming (OTP) –> Not much use in development and prototyping environments.
4. Their interconnection structure is “rad hard”, or relatively immune to the effects of radiation the configuration data is buried deep inside them.
5. Unfortunately, the technology used to fabricate anti-fuse FPGAs is one or more generations behind the technology used for SRAM versions.

Question 33

FPGA Technologies -

E-PROM-based (8)

Answer 33

1. Configuration cells are connected together in a long shift-register-style chain (scan chain).
2. Programming done off line, some allow in-system programming (ISP).
3. Use charged floating gates, programmed by a high voltage.
4. Reprogrammable and non-volatile.
5. Programming time is about 3 times longer than SRAM version.
6. Have high static power because of the internal pull-up resistors.
7. For security, some use a multibit key (50 to several hundred bits)
8. Disadvantage:
   (a) The devices require about 5 additional
   process steps beyond the standard CMOS
   process.
   (b) Similar to anti-fuse, this cause a lag of these devices, technology wise.

Question 34

FPGA Technologies -

SRAM-based (5)

Answer 34

1. Mainly uses CMOS transmission gates to establish interconnect.
2. Status of the gates is determined by contents of SRAM configuration memory.
3. The majority use SRAM based configuration cells, which allows fast reconfiguration:
   (a) Allows new design ideas to quickly
   implemented and tested.
   (b) Allows evolving standards and protocols to be accommodated.
   (c) Allows the FPGA to carry out multiple functions such as self-tested or board/system test at power-up and something else later.
4. Another disadvantage - SRAM technology is very heavily invested in, and therefore, FPGA companies can leverage this
   - The same process used to fabricate the logic gates on the FPGA is used to fabricate SRAM –> no special processing steps are needed.
5. Disadvantage:
   (a) In terms of volatility, which is overcome with a special external memory device or microprocessor (costly either way).
   (b) Can be difficult to protect your intellectual property –> the configuration file maybe somewhere on disk, in memory, etc.
   –> SOLUTION: use bitstream encryption.

Question 35

Comparison between types of FPGAs:

Answer 35

Refer to pic in Final FPGA folder.

Question 36

Current FPGA Structure:

Answer 36

Refer to pic in Final FPGA folder.

Question 37

FPGA Structure - Common Features
<> :
(3)

Answer 37

1. Basic logic unit in an FPGA.
2. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 5 inputs, some selection circuitry (MUX, etc.), and flip-flops.
3. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM.

Question 38

Inner Structure of Configurable Logic Block (CLB):

Answer 38

Refer to pic in Final FPGA folder.

Question 39

FPGA Structure - Common Features
<> :
(3)

Answer 39

1. Provides the ideal interface bridge in the system.
2. Grouped in banks with each bank independently able to support different I/O standards.
3. FPGA nowadays have dozen I/O banks, thus allowing flexibility in I/O support.

Question 40

Inner Structure of SelectIO (IOB):

Answer 40

Refer to pic in Final FPGA folder.

Question 41

FPGA Structure - Common Features
Interconnect:
(3)

Answer 41

1. Flexible interconnect routing routes the signals between CLBs and to and from I/Os.
2. Various types of routing;
   (a) from that designed
   to interconnect
   between CLBs to
   fast horizontal and
   vertical long lines
   spanning the device
   to global low-skew
   routing for Clocking
   and other global
   signals.
3. Design software makes the interconnect routing task hidden
   to the user unless specified otherwise, thus significantly
   reducing design complexity.

Question 42

FPGA Structure - Common Features
Memory:
(2)

Answer 42

1. Embedded Block RAM memory is available inmost FPGAs.

2. Allows for on-chip memory for your design.

Question 43

FPGA Structure - Common Features
Digital Clock Management:
(2)

Answer 43

1. Provided by most FPGAs in the industry.
   2The most advanced FPGAs from Xilinx offer both digital clock
   management and phase-looped locking that provide precision
   clock synthesis combined with jitter reduction and filtering.

Question 44

FPGA STRUCTURE – Altera Stratix II

Answer 44

Refer to pic in Final FPGA folder.

Question 45

FPGA vs ASIC - Design Advantage

Answer 45

Refer to pic in Final FPGA folder.

Question 46

FPGA vs ASICs Design Flow

Answer 46

Refer to pic in Final FPGA folder.

Question 47

Rapid prototyping with Verilog and FPGA (Definition)

Answer 47

Create a working prototypes as quickly as possible using FPGA with Verilog as the design entry.

Question 48

Rapid prototyping with Verilog and FPGA (Advantages)

Answer 48

1. It bypass the structural detail that is forced by schematic-based
   entry method.
2. Allows usage of single clock –> timing-driven routing tools works more efficient.
3. FPGA register-rich –> recommended to employ one-hot encoding in state machines –> produce simpler NS & output logic.

Question 49

Rapid prototyping with Verilog and FPGA

Answer 49

Refer to pic in Final FPGA folder