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assembly > chapter 2 -X86 Processor Architecture > Flashcards

chapter 2 -X86 Processor Architecture Flashcards

1
Q

What unit synchronizes CPU operations in a microcomputer?

A) Arithmetic & Logic Unit
B) Memory Storage Unit
C) Clock
D) Data Bus

A

C) Clock

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2
Q

The measurement unit of a clock is:

A) Cycles
B) Hertz (Hz)
C) Seconds
D) Instructions per second

A

B) Hertz (Hz)

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3
Q

What type of memory responds faster to the CPU?

A) Static RAM
B) Dynamic RAM
C) ROM
D) Video RAM

A

A) Static RAM

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4
Q

A cache hit occurs when:

A) Data is not found in memory
B) Data is already in the cache memory
C) Data is corrupted
D) Data is read from disk

A

B) Data is already in the cache memory

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5
Q

IA-32 is also referred to as:

A) i386
B) x86-64
C) ARM32
D) 8086

A

A) i386

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6
Q

Which x86 mode is used for multitasking in modern systems?

A) Real-Address Mode
B) Protected Mode
C) Virtual-8086 Mode
D) System Management Mode

A

B) Protected Mode

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7
Q

In Real-Address Mode, the maximum addressable memory is:

A) 4 GB
B) 1 MB
C) 2 GB
D) 64 KB

A

B) 1 MB

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8
Q

Which register is commonly used as a loop counter?

A) EAX
B) ECX
C) ESP
D) EIP

A

B) ECX

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9
Q

The formula for calculating a linear address is:

A) Segment × 20 + Offset
B) Segment × 16 + Offset
C) Segment × 32 + Offset
D) Offset × 16 + Segment

A

B) Segment × 16 + Offset

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10
Q

Paging divides memory into blocks called:

A) Segments
B) Frames
C) Pages
D) Tables

A

C) Pages

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11
Q

Virtual memory manager issues a ___ when a page needs to be loaded from disk:

A) Cache miss
B) Page fault
C) System interrupt
D) Exception

A

B) Page fault

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12
Q

The EAX register is typically used for:

A) Addressing
B) Loop control
C) Accumulation
D) Stack pointer

A

C) Accumulation

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13
Q

The EIP register holds:

A) Current stack pointer
B) Instruction pointer
C) Loop counter
D) Segment selector

A

B) Instruction pointer

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14
Q

Which flag is set when a result is zero?

A) Carry
B) Overflow
C) Zero
D) Parity

A

C) Zero

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15
Q

Which register contains status and control flags?

A) EAX
B) ECX
C) EFLAGS
D) ESP

A

C) EFLAGS

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16
Q

BIOS functions operate at which programming level?

A) Level 3
B) Level 2
C) Level 1
D) Level 0

A

C) Level 1

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17
Q

Serial communication transmits:

A) Multiple bits simultaneously
B) One bit at a time
C) Only ASCII data
D) Only binary data

A

B) One bit at a time

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18
Q

FireWire supports a maximum speed of:

A) 800 MB/s
B) 1 GB/s
C) 5 GB/s
D) 400 MB/s

A

A) 800 MB/s

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19
Q

What component handles the loading and unloading of pages in memory?

A) BIOS
B) Cache Manager
C) Virtual Memory Manager
D) Paging Unit

A

C) Virtual Memory Manager

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20
Q

Dual-port memory optimized for video refresh is:

A) ROM
B) VRAM
C) DRAM
D) SRAM

A

B) VRAM

21
Q

What is the role of the clock in a processor?

A

The clock synchronizes all CPU operations by providing a consistent timing signal, measured in hertz (Hz), ensuring instructions execute in a predictable sequence.

22
Q

What is a “cache hit,” and why is it important for system performance?

A

A cache hit occurs when the requested data is found in the CPU’s cache memory. It improves performance by avoiding slower main memory access.

23
Q

Describe the difference between Real-Address Mode and Protected Mode.

A

Real-Address Mode: This mode operates similarly to early microprocessors, where the CPU can address up to 1 MB of memory using direct addressing. It lacks advanced features like multitasking or virtual memory.
Protected Mode: Introduced with the 80286 processor, this mode supports multitasking, virtual memory, and access control, allowing for more efficient and secure use of system resources.

24
Q

How is a linear address calculated using segment and offset?

A

Linear Address = Segment Address × 16 + Offset.

25
Q

What is the purpose of the ECX register in the x86 architecture?

A

The ECX register is commonly used as a loop counter in repetitive operations. It is decremented automatically in some instructions, such as LOOP, and helps control the number of iterations in a loop.

26
Q

Define the term “page fault” and its significance in memory management.

A

A page fault occurs when the CPU tries to access a memory page that is not currently loaded in physical RAM. The Virtual Memory Manager (VMM) handles this by loading the required page from secondary storage into RAM. Page faults are essential for virtual memory systems, enabling efficient use of physical memory.

27
Q

List the three levels of programming for input-output operations.

A

Level 0: Direct hardware access using machine instructions (e.g., IN, OUT).
Level 1: BIOS-level operations, providing basic input-output routines for devices.
Level 2: Operating system-level operations, offering high-level access to I/O devices through drivers.

28
Q

What does the EIP register store during program execution?

A

The EIP (Instruction Pointer) register stores the memory address of the next instruction to be executed. It is automatically updated after each instruction to point to the following one.

29
Q

Explain the function of the Global Descriptor Table (GDT) in Protected Mode.

A

The Global Descriptor Table (GDT) is a data structure used in Protected Mode to define the characteristics of memory segments, such as base address, size, and access privileges. It ensures proper memory management and security by controlling access to memory segments.

30
Q

How does the Virtual Memory Manager (VMM) handle paging in a multitasking system?

A

The VMM divides physical memory into fixed-size blocks called pages. When a program accesses a page not in physical memory, the VMM issues a page fault, retrieves the required page from disk, and places it in RAM. It also manages page replacement to optimize memory use in a multitasking environment.

31
Q

Which type of memory has the fastest response time to the CPU? (*)

A) Static RAM (SRAM)
B) Dynamic RAM (DRAM)
C) ROM
D) Cache Memory

A

Cache Memory

32
Q

What occurs when data is retrieved directly from the cache? (*)

A) Cache hit
B) Cache miss
C) Page fault
D) Buffer overflow

A

A) Cache hit

33
Q

The IA-32 architecture’s Protected Mode enables: (*)

A) Multitasking and virtual memory
B) Real-time applications only
C) Single-tasking environments
D) Compatibility with legacy systems

A

A) Multitasking and virtual memory

34
Q

Virtual-8086 mode is a feature of which x86 mode? (*)

A) Real-Address Mode
B) Protected Mode
C) System Management Mode
D) Long Mode

A

B) Protected Mode

35
Q

Paging is used in which x86 mode? (*)

A) Real-Address Mode
B) Virtual-8086 Mode
C) Protected Mode
D) Long Mode

A

C) Protected Mode

36
Q

A page fault occurs when: (*)

A) Data is found in the cache
B) Data is accessed in virtual memory
C) The required page is not in physical memory
D) Memory is corrupted

A

C) The required page is not in physical memory

37
Q

The EAX register is used for: (*)

A) General arithmetic and data storage
B) Addressing
C) Stack operations
D) Loop control

A

A) General arithmetic and data storage

38
Q

Which register holds the address of the next instruction? (*)

A) ESP
B) ECX
C) EFLAGS
D) EIP

A

D) EIP

39
Q

Which flag indicates an overflow has occurred in arithmetic operations? (*)

A) Zero Flag
B) Carry Flag
C) Overflow Flag
D) Sign Flag

A

C) Overflow Flag

40
Q

The purpose of the EFLAGS register is to: (*)

A) Track loop iterations
B) Control system interrupts
C) Store the status of operations
D) Hold the instruction pointer

A

C) Store the status of operations

41
Q

A stack is typically accessed using which register? (*)

A) ESP
B) EBP
C) ECX
D) EAX

A

A) ESP

42
Q

Hyper-threading in modern processors allows: (*)

A) Faster clock speeds
B) Multithreading in a single core
C) Access to virtual memory
D) Error correction in data transfers

A

B) Multithreading in a single core

43
Q

Pipelining improves CPU performance by: (*)

A) Increasing clock speed
B) Running multiple instructions in parallel stages
C) Reducing power consumption
D) Using more cache memory

A

B) Running multiple instructions in parallel stages

44
Q

Explain Real-Address Mode in x86 processors.

A

Real-Address Mode is the simplest operating mode, allowing access to 1 MB of memory with direct addressing, often used for legacy software compatibility.

45
Q

What is the primary use of the EAX register?

A

EAX is the primary accumulator used for arithmetic operations and data manipulation in x86 processors.

46
Q

What is the purpose of the EIP register?

A

EIP (Instruction Pointer) holds the address of the next instruction to be executed.

47
Q

What is the function of the EFLAGS register?

A

EFLAGS stores the status of arithmetic operations (e.g., Zero, Carry) and controls CPU operations.

48
Q

What is the difference between SRAM and DRAM?

A

SRAM is faster and used for cache memory, while DRAM is slower but more cost-effective and used for main memory.

49
Q

How does hyper-threading improve CPU performance?

A

Hyper-threading enables a single CPU core to execute multiple threads simultaneously, improving multitasking efficiency.

assembly (3 decks)

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