Architectures Flashcards

1
Q

What is CISC RISC debate

A

Debate considering how to split relative complexities and size of hardware and software

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2
Q

CISC

A

Complex instruction set. A large instruction set to accomplish tasks in as few lines of assembly language as possible.
Complex processor hardware needs to be designed as it can understand and execute the series of subtasks that make up a single complex instruction.
Chipmakers provide a rich set of high level instructions to code with.

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3
Q

How to distinguish CISC

A

Combining load/store with calculation

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4
Q

Registers in CISC

A

Less registers to make space for complex decoder so data has to move about more in memory

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5
Q

Cycles in CISC and RISC

A

CISC- a single instruction may take more than one cycle

RISC- a single instruction takes one clock cycle

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6
Q

Memory movement for CISC

A

More movement in and out of CPU because fewer registers so often a bottleneck

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7
Q

Coding and compiling CISC

A

Code is small, tight and easy to write. Compiler generates a single complex machine code instruction to achieve task

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8
Q

RISC reduced instruction set computers

A

A relatively simple CPU decoder with more registers at the expense of having to write more lines of code to do the same thing

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9
Q

RISC allows…

A

Parallel processing so performance improves e.g. LDA A and LDA B are independent

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10
Q

Who provide RISC

A

ARM

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11
Q

Who provide CISC

A

AMD and INTEL

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12
Q

CISC is better for and RISC is better for…

A

CISC: complex maths
RISC: basic calculations and comparing (faster for this)

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13
Q

CISC v RISC

A
  • CISC more complex hardware
  • CISC more addressing modes
  • CISC has more compact software code v more complicated software code
  • CISC has more instructions v limited instructions available
  • CISC has variable sized bytes, RISC has a fixed number
  • CISC uses less ram to store a program v more ram
  • CISC fewer registers so more RAM used for intermediate results v more registers so less RAM movement
  • Each instruction takes multiple cycles v each instruction takes one cycle each
  • RISC = pipelining is possible
  • RISC = more addressing modes
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14
Q

Why programs run faster for RISC

A

Because simpler instructions, each taking one clock cycle

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15
Q

Define co-processor

A

An extra processor used to supplement the functions of a primary processor , generally carrying out a limited range of functions. Not a general purpose processor able to fetch its own instructions

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16
Q

Computers first built

A

1940s and 50s

17
Q

Pioneers of computers

A

Turing and Von Neumann

18
Q

Von Neumann machine key idea

A

Not only program but data being processed by program should be stored in the same memory. Data and instructions should share the same memory and buses
Stored program concept:
Machine code instructions are fetched decoded and executed serially, one at a time by a processor that performs logical and arithmetic operations. The program must be resident in main memory to be executed

Same data (and address) bus for (address of) instructions and data
Same word length for all memory: instructions and data
19
Q

Harvard key idea

A

Memory split into two parts which are physically separate, one for data and one for memory

20
Q

Why is Harvard better than Von Neumann

A

Faster as data and instructions fetched in parallel rather than competing for same bus

21
Q

The two memories in Harvard

A

Are physically separate and can have different characteristics e.g. Data in read write and instructions in read only for embedded
E.g. Instructions have more memory with wider bus and word size

22
Q

Harvard used extensively with

A

Digital signal processing: embedded e.g. Audio and image processing, sonar processing, radar processing, biomedical processing

23
Q

disadv of coprocessors

A

take up motherboard space, more expensive, uses a lot of power, limited by applications ability to take adv

24
Q

GPU

A

a co-processor used for offloading computer intensive parts of an application. It has a massively parallel architecture consisting of smaller, more efficient cores to handle tasks simultaneously (vs optimised for sequential serial processing.) Suitable for processing large blocks of visual data simultaneously and manipulating computer graphics and image processing.