8085 PART 2

Question 1

List the Control and Status Signals

Answer 1

ALE
WR
RD
IO/M
S1 and S0

Question 2

Describe ALE signal

Answer 2

-Address Latch Enable: This is a positive going pulse
generated every time the 8085 begins and operation (machine cycle); it indicates that the bits on AD7 − AD0 are address bits.

Question 3

Describe RE signal

Answer 3

Read: This is a Read control signal (active low). This signal indicates that the selected I/O or memory device is to be read and data is available on the data bus.

Question 4

Describe the WR signal

Answer 4

Write: This is a Write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O

Question 5

Describe the IO/M signal

Answer 5

This is a status signal used to differentiate between I/O and memory operations. When High-it is I/O operations. When low it indicates memory operations. This signal combines with WR and RD to generate memory and I/O operation.

Question 6

Describe the S1 and S2 signals

Answer 6

These are status signals similar to IO/M can be used to identify different operations.

Question 7

Draw a table showing the 8085 Machine Cycle Status and Control Signals

Answer 7

See page 41

Question 8

Describe the Power Supply and Clock Frequency part of the 8085

Answer 8

VCC: +5V power supply
VSS: Ground reference
X1, X2 Crystal clock- 6 MHz
CLK(OUT): Clock output: This signal can be used as the system clock for other devices

Question 9

List the Interrupts and externally initiated signals

Answer 9

INTR(input)
INTA (Output)
RST 7.5,RST 6.5, RST 5.5(Inputs)
TRAP Input (Input)
HOLD (Input)

Question 10

Describe the INTR(input)

Answer 10

Interrupt request: this is used as a general purpose
interrupt

Question 11

Describe the INTA (Output)

Answer 11

Interrupt acknowledge: This is used to
acknowledge interrupt

Question 12

Describe the RST 7.5,RST 6.5, RST 5.5(Inputs)

Answer 12

Restart Interrupts: These are vectored interrupts that transfer the program control to specific locations. They have higher priorities than the INTR
interrupts. Among these three, the priority is 7.5,6.5,5.5

Question 13

Describe the TRAP Input (Input)

Answer 13

This is a nonmaskable interrupt and has the
highest priority

Question 14

Describe the HOLD (Input):

Answer 14

This signal indicates that a peripheral such as a
DMA (Direct Memory Access) controller is requesting the use of the address and data buses.

Question 15

Describe the HLDA (Output)-

Answer 15

Hold Acknowledge: This signal acknowledge
the HOLD request.

Question 16

Describe the Ready (Input):

Answer 16

This signal is used to delay the microprocessor
READ and WRITE cycles until a slow responding peripheral is ready to send or accept data. When this signal goes low, the microprocessor waits for a number of clock cycles until it goes high.

Question 17

Describe RESETIN:

Answer 17

When the signal on this pin goes low, the program
counter is set to zero and the MPU is reset.

Question 18

Describe RESETOUT:

Answer 18

This signal indicates that the MPU is being reset