4-1 Buses

Question 1

2Mx8 memory would require how many bits to store the addresses in a byte-addressable architecture?

Answer 1

21

Question 2

Which of the following is the least likely to be found inside a computer’s CPU?

Answer 2

Main Memory

Question 3

Which of the following buses most commonly interconnects other buses?

Answer 3

Backplane Bus

Question 4

Which of the following components of a bus is most likely to transmit the content of a memory location from main memory to the CPU?

Answer 4

Data Lines

Question 5

Which of the following components of a bus is most likely to transmit the binary sequence for a memory location?

Answer 5

Address Line

Question 6

Synchronous clock time on buses connected to the CPU almost always match the CPU clock time.

Answer 6

False

Question 7

If memory is 8 bits wide, changing from byte-addressed memory to word-addressed memory in a 16 bit word-length architecture will

Answer 7

Halve the number of required addresses

Question 8

Interrupts that occur regularly at a time interval or at a consistent location in a program are

Answer 8

Synchronous

Question 9

Explain the purpose of an arbiter in centralized parallel bus arbitration.

Answer 9

The arbiter grants access to the bus. With centralized parallel arbitration, all bus-connected devices will have a request line to the arbiter, and the arbiter will have a mechanism for determining priority. Grants to the bus will flow over grant lines.

Question 10

Explain what allowing the block transfer of multiple words on a bus means. What advantages are gained by allowing the block transfer of multiple words on a bus?

Answer 10

Block transfer of words means that a device can advertise how many words need to be sent, and it can requests bus access for multiple sequential cycles. Connected devices need to request the bus less frequently if multiple words needs to be sent.