3-5 Sequential Circuits

Question 1

An SR flip-flop in state 0 will change to state 1 upon setting the reset line to 1.

Answer 1

False

Question 1

The primary benefit of a clocked D flip-flop over a clocked SR latch is the ability to

Answer 1

Prevent the metastable state

Question 2

An inverting buffer with a control line value of 1 and a data in of 1 will output

Answer 2

0

Question 2

SR flip-flop states are named for the value of Q-bar.

Answer 2

False

Question 3

A non-inverting buffer with a control line value of 0 and a data in of 1 will output

Answer 3

Disconnect

Question 3

With both the set and reset values set to 0, an SR flip-flop will have a Q value of

Answer 3

0 or 1 depending on the last powered set or reset line

Question 4

A CS value of 0, RD value of 1, and an OE value of 1 would cause what operation?

Answer 4

Neither

Question 5

A CS value of 1, RD value of 0, and an OE value of 1 would cause what operation?

Answer 5

Write

Question 6

An address of 00 would select word line

Answer 6

0