1.2 Computer-System Organization Flashcards
A modern general-purpose computer system consists of one or more _____ and a number of device controllers.
CPUs
Device controllers are connected through a common _____ that provides access between components and shared memory.
bus
Each device controller is in charge of a specific type of _____, such as a disk drive or graphics display.
device
A device controller maintains some local _____ storage.
buffer
The device controller is responsible for moving the data between the peripheral devices and its local _____ storage.
buffer
Typically, operating systems have a _____ for each device controller.
device driver
The device driver provides the rest of the operating system with a uniform _____ to the device.
interface
The CPU and device controllers can execute in _____, competing for memory cycles.
parallel
To ensure orderly access to shared memory, a memory controller _____ access to the memory.
synchronizes
The three key aspects of the system discussed are interrupts, storage structure, and _____ structure.
I/O
To start an I/O operation, the device driver loads the appropriate registers in the _______.
device controller
The device controller examines the contents of the registers to determine what action to take, such as _______.
read a character from the keyboard
Once the transfer of data is complete, the device controller informs the device driver that it has _______.
finished its operation
The device driver gives control to other parts of the operating system, possibly returning the data or a _______ to the data if the operation was a read.
pointer
For other operations, the device driver returns status information such as ‘write completed successfully’ or _______.
‘device busy’
The controller informs the device driver that it has finished its operation via an _______.
interrupt
Hardware may trigger an interrupt by sending a signal to the CPU, usually by way of the _______.
system bus
When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a _______ location.
fixed
The interrupt service routine executes, and on completion, the CPU resumes the _______ computation.
interrupted
Each computer design has its own interrupt mechanism, but several functions are _______.
common
The straightforward method for managing the transfer of control to the interrupt service routine would be to invoke a _______ routine.
generic
Interrupts must be handled quickly, as they occur very _______.
frequently
A table of pointers to interrupt routines can be used to provide the necessary _______.
speed
The table of pointers is generally stored in _______ memory.
low
These locations hold the addresses of the _______ service routines for the various devices.
interrupt
This array, or interrupt vector, of addresses is indexed by a unique number given with the _______ request.
interrupt
The interrupt architecture must also save the _______ information of whatever was interrupted.
state
If the interrupt routine modifies the processor state, it must explicitly save the _______ state.
current
After servicing the interrupt, the saved return address is loaded into the _______ counter.
program
The CPU detects a signal on the interrupt-request line after executing every ___.
instruction
The CPU reads the ___ when it detects that a controller has asserted a signal.
interrupt number
The CPU jumps to the interrupt-handler routine using the interrupt number as an index into the ___.
interrupt vector
The interrupt handler saves any state it will be changing during its ___.
operation
After processing, the interrupt handler executes a ___ to return the CPU to the execution state prior to the interrupt.
return from interrupt instruction
The device controller raises an interrupt by asserting a signal on the ___.
interrupt request line
In a modern operating system, we need the ability to defer interrupt handling during ___.
critical processing
An efficient way to dispatch to the proper interrupt handler for a device is a requirement of modern operating systems, known as ___.
efficient dispatching
Modern computer hardware provides multilevel interrupts, allowing the operating system to distinguish between ___ and ___ interrupts.
high-priority, low-priority
The nonmaskable interrupt is reserved for events such as ___.
unrecoverable memory errors
The second interrupt line is ___, which can be turned off by the CPU before executing critical instructions.
maskable
The purpose of a vectored interrupt mechanism is to reduce the need for a single interrupt handler to search all possible ___ of interrupts.
sources
A common solution to the interrupt handler address limitation is to use ___.
interrupt chaining
In interrupt chaining, each element in the interrupt vector points to the head of a list of ___.
interrupt handlers
Events from 0 to 31 are used to signal various error conditions and are classified as ___.
nonmaskable
Events from 32 to 255 are classified as ___ and are used for device-generated interrupts.
maskable
The interrupt mechanism implements a system of interrupt ___ levels.
priority
The system of interrupt priorities allows a high-priority interrupt to ___ the execution of a low-priority interrupt.
preempt
Interrupts are used throughout modern operating systems to handle ___ events.
asynchronous
Because interrupts are used heavily for time-sensitive processing, efficient interrupt handling is required for good system ___.
performance
The CPU can load instructions only from _______.
memory
Main memory is also called _______.
random-access memory (RAM)
Main memory is commonly implemented in a semiconductor technology called _______.
dynamic random-access memory (DRAM)
The first program to run on computer power-on is called a _______.
bootstrap program
Since RAM is ________, it cannot be trusted to hold the bootstrap program.
volatile
For nonvolatile storage, computers use _______.
electrically erasable programmable read-only memory (EEPROM)
EEPROM can be changed but cannot be changed _______.
frequently
The load instruction moves a byte or word from main memory to an _______ within the CPU.
internal register
The store instruction moves the content of a register to _______.
main memory
In a von Neumann architecture, the instruction-execution cycle first fetches an instruction from _______.
memory
Main memory is usually too small to store all needed programs and data _______.
permanently
The most common secondary storage devices are _______ and _______.
hard-disk drives (HDDs), nonvolatile memory (NVM) devices
Secondary storage is _______ than main memory.
much slower
Tertiary storage is used only for special purposes, such as _______.
to store backup copies of material
The main differences among various storage systems lie in _______, ________, and _______.
speed, size, volatility
The various storage systems can be organized in a hierarchy according to _______ and _______.
storage capacity, access time
Volatile storage is referred to simply as _______.
memory
Nonvolatile storage retains its contents when power is _______.
lost
Mechanical storage systems include _______ and _______.
HDDs, optical disks
Electrical storage systems include _______ and _______.
flash memory, SSD
Mechanical storage is generally larger and less expensive per byte than _______ storage.
electrical
The design of a complete storage system must balance all factors, including the use of _______ memory as necessary.
expensive
Caches can be installed to improve performance where a large disparity exists between two _______.
components
A large portion of operating system code is dedicated to managing _______.
I/O
The form of _______ I/O is fine for moving small amounts of data.
interrupt-driven
Direct memory access (DMA) is used to solve the problem of high overhead when used for _______ data movement.
bulk
In DMA, the device controller transfers an entire block of data directly to or from the device and _______.
main memory
Only one _______ is generated per block in DMA to indicate that the operation has completed.
interrupt
While the device controller is performing DMA operations, the CPU is available to accomplish _______.
other work
Some high-end systems use _______ rather than bus architecture.
switch
On switch architecture systems, multiple components can talk to other components _______.
concurrently
In switch architecture, DMA is even more _______.
effective
