1.1a/b - The CPU & Fetch, Decode, Execute Cycle

Question 1

The Control unit

Answer 1

Directs the flow of data and information into the CPU. Additionally, it controls other parts of the CPU.

Question 2

Arithmetic and Logic Unit
(ALU)

Answer 2

It performs simple calculations and logical operations. Additionally acts as a ‘revolving door’ for data going into and out of the CPU.

Question 3

Registers

Answer 3

The registers and temporary storage spaces for data and instructions in the CPU. The registers are used during the FDE Cycle.

Question 4

Program Counter
(PC)

Answer 4

A register that tracks the RAM address of the next instruction to be fetched.

Question 5

Memory Address Register
(MAR)

Answer 5

A register that tracks the RAM address of data that is currently being accessed.

Question 6

Memory Data Register
(MDR)

Answer 6

A register that stores the data that is transferred from the RAM to the CPU.

Question 7

Current Instruction Register
(CIR)

Answer 7

A register that stores the information that has been fetched from RAM, and is about to be decoded or executed.

Question 8

Accumulator
(ACC)

Answer 8

The ACC stores the results of executions performed in the FDE cycle.

Question 9

Explain the process of the FDE cycle
(7 Points)

Answer 9

1. The Program Counter (PC) register displays the address in RAM of the next instruction to be processed.
2. The PC register is increased by 1. This prepares the CPU for the next instruction to be fetched.
3. The CPU checks the address in RAM which matches the address held in the MAR.
4. The instruction in RAM is transferred to the Memory Data Register (MDR).
5. The instruction in the MDR is copied into the Current Instruction Register (CIR).
6. The instruction in the CIR is decoded and executed. Any result of and execution is stored in the Accumulator (ACC).
7. The cycle repeats by returning to the first step and checking the program counter for the address of the next instruction.

Question 10

Address Bus

Answer 10

Sends a memory address of where data is stored. The address is sent from the CPU to the RAM during the FDE cycle.

Question 11

Data bus

Answer 11

Transfers data between components. Data is sent both ways.

Question 12

Control bus

Answer 12

Sends control signals from the control unit to other components of the system. Status signals are sent back to the CPU.

Question 13

State the function of the opcode and operand

Answer 13

The opcode specifies the instruction to be
performed and the addressing mode. The
operand holds a value which is related to the
data on which the instruction is to be
performed.

Question 14

Instruction set

Answer 14

The possible number of instructions that the CPU can understand and decode