1.1.1) Structure and function of the processor Flashcards
(a) The Arithmetic and Logic Unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR). Buses: data, address and control: how this relates to assembly language programs. (b) The Fetch-Decode-Execute Cycle; including its effects on registers. (c) The factors affecting the performance of the CPU: clock speed, number of cores, cache. (d) The use of pipelining in a processor to improve
What is the ALU and what is it’s role?
Arithmetic Logic Unit, it performs all calculations and logical operations
What are some functions of the ALU? (4)
Addition, subtraction, multiplication and division
Logical bitwise operations- AND, OR, NOT and XOR
Comparisons between values, such as greater than, less than, equal to.
Shifting binary patterns to the left or right.
What is the CU?
the Control Unit
What are the functions of the CU? (5)
Controls the inputs and outputs of the CPU
Directs the flow of data
Sends and receives control signals to and from other components
Decodes instructions
Manages the timing of data flow around the system
What are the different registers? (7)
GPRs (General Purpose registers)
PC (Program Counters)
CIR (Current Instruction registers)
SR (Status register)
MAR (Memory Address register)
MDR (Memory Data register)
Accumulator
Describe the role of GPRs…
Used as temporary storage registers to speed up processing instead of having to access RAM every time. GPRs are used by the ALU to store results of intermediate calculations produced as part of a larger computation.
Describe the role of the Program Counter…
Holds the address of the next instruction to be executed
Describe the role of the Current Instruction Register….
Holds the current instruction being executed.
Describe the role of the Status register…
Used to store any indicators such as errors or exceptions. It allows or disables interrupts to be raised. It brings attention to things like incomplete calculations or hardware malfunctions
Describe the role of the MAR….
temporarily holds the address of the data in RAM needing to be read/written to.
Describe the role of the MDR…
temporarily holds the data value retrieved from the address held in the MAR.
Describe the role of the accumulator…
Stores the result of ALU’s calculations. The processor accesses other GPRs where temporary values are stored while calculations are completed. Any result resides in the accumulator.
What are the 3 types of buses? (3)
Data bus, Address bus, Control bus
What does the data bus do? (4)
(where does it transfer between?, which directions?, what do the parallel lines mean?, why can it affect CPU performance?)
The data bus transfers between I/O, the CPU, main memory and secondary storage devices.
Each line is bidirectional meaning data can be read/written from.
The amount of parallel lines correlates with the number of bits able to be transferred in one operation.
The quantity able to be transferred can affect the CPU performance
What does the Address Bus do? (3)
(what does it hold?, what is the width?, what does the width determine?)
Holds the location of where data instructions are held.
The number of parallel lines determines the number of bits that can be used to form an address.
The width determines the maximum number of addressable memory locations i.e the maximum memory capacity of a computer system. This is called the address space and can effect processor performance.
What does the Control bus do?
Sends control signals that manage and orchestrate operations.
It manages instructions outside of the CPU.
It is bi directional as it needs access to all components in order to coordinate them.
What is the FDE cycle?
The fetch decode execute cycle is the cycle with 3 main stages which every time an instructor is carried out it goes through the three tables.
What happens in the Fetch part of the FDE Cycle? (4)
- Address in PC copied to MAR
- PC incremented to “point” to next instruction
- Instruction found at address held in MAR copied to MDR
- Instruction in MDR copied to CIR
What happens in the Decode part of the FDE Cycle? (1)
- CU decodes the contents of the CIR
What happens in the Decode part of the FDE Cycle? (1)
- CU sends signals to relevant components
What are the factors that affect the CPU? (3)
Clock speed, number of cores, cache
What is the system clock? (3)
The clock generates a series of signals (0->1 when starting an instruction and 1-> 0 when ending)
This happens several million times per second.
The CPU cannot perform any faster than this.
How does clock speed effect CPU performance?
The greater the clock speed the faster instructions can be executed.
1GHz= ?
One billion clock cycles per second
What is overclocking?
Overclocking is increasing the clock speed beyond what is set by the manufacturer, producing excess heat which must be cooled.
What is a core?
Each core is a CPU
How does the number of cores effect CPU performance?
In theory the more cores the more instructions can be processed simultaneously however in reality software often cannot take advantage of all of these.
What is cache? (3)
Small very fast and expensive memory that lives in the CPU.
Instructions fetched from main memory are copied into cache to be used again if needed.
These are often renewed as more instructions are used.
How does cache affect CPU performance?
The more cache memory a computer has, the faster it runs.
What does Von Neumann architecture include?
The basic components of the computer and processor (e.g. single control unit, ALU, register and memory units)
Which processor uses a linear format and what is that?
Von Neumann
A linear format means that each cycle must finish so the next one can begin.
What is a key characteristic of the Vonn Neumann Architecture?
There is a shared memory and shared data bus used for both data and instructions.
What is Von Neumann bottleneck?
The data bus is a lot slower than the rate at which the CPU can carry out instructions so there is a bottleneck.
What is the structure of the Harvard architecture?
Has physically separate memories of instructions and data.
What is Harvard architecture most commonly used for?
Embedded processors
What does Harvard architecture allow you to optimize?
The size of individual memory cells and their buses depending on your needs.
What is pipelining?
Pipelining is a technique used to improve processor performance. It means an instruction can simultaniously be fetchedwhile the previous instruction is decoded and the one before that is executed.
What needs to happen to use pipelining?
The task needs to be broken down into subtasks.
Where can this be used?
This can be used in many parts of a computer system but particularly in the FDE cycle.
Why is pipelining used in the FDE cycle?
- As the FDE cycle contains many distinct, repeated stages.
- There are registers between these stages which keep intermediate results.
- The clock signal synchronises the flow of data.
- This improves performance as registers are not overwritten.
In LMC, why do BRP and BRZ instructions cause issues with pipelining?
In BRP and BRZ instructions there are two possible outcomes. The correct outcome can not be determined until execution, this means if pipelining is used the CPU could fetch/decode the wrong instruction causing disruption.
What is a register?
A small amount of high-speed memory contained in the CPU.
What are the different uses of the Accumulator:
