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Computer Science 1.1 - Components of a Computer > 1.1.1: Structure and Function of the Processor > Flashcards

1.1.1: Structure and Function of the Processor Flashcards

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1
Q

What does the Arithmetic Logic Unit do to the data?

A
  • Performs arithmetic and logical operations on the data
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2
Q

What instructions can the Arithmetic Logic Unit do?

A
  • ADD
  • SUBTRACT
  • MULTIPLY
  • DIVIDE
  • On fixed or floating point numbers
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3
Q

What operations can the Arithmetic Logic Unit do?

A
  • Shift operations comparing two values
  • Using AND, OR, NOT, XOR
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4
Q

What does the Control Unit do?

A
  • Controls and coordinates the activities of the CPU
  • Directs the flow of data between CPU and other devices
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5
Q

What does the Control Unit do to the next instruction?

A
  • Accepts the next instruction
  • Decodes it into several sequential steps [e.g. fetching addresses and data from memory]
  • Manages its execution
  • Stores the resulting data back in memory or registers
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6
Q

What are Registers?

A
  • A small amount of very high speed memory
  • Used to temporarily store data, and all arithmetic, logical, and shift operations
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7
Q

What is the purpose of the Program Counter?

A
  • Holds address of the next instruction to be executed
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8
Q

What is the purpose of the Accumulator?

A
  • Stores results from calculations
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9
Q

What is the purpose of the Memory Address Register?

A
  • Holds address of a location that is to be read from or written to
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10
Q

What is the purpose of the Memory Data Register?

A
  • Temporarily stores data that has been read or data that needs to be written
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11
Q

What is the purpose of the Current Instruction Register?

A
  • Holds the current instruction being executed, divided up into operand and opcode
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12
Q

What are Buses?

A
  • A set of parallel wires connecting two or more components inside the CPU
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13
Q

What is the width of a Bus?

A
  • The number of parallel wires the bus has
  • Typically 8, 16, 32, or 64 wires wide
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14
Q

What is the width of a Bus directly proportional to?

A
  • Directly proportional to the number of bits that can be transferred simultaneously at any given time
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15
Q

What is the Data Bus?

A
  • Bi-directional bus used for transporting data and instructions between components
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16
Q

What is the Address Bus?

A
  • Uni-directional bus used to transmit the memory addresses specifying where data is to be sent to or retrieved from
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17
Q

What is the width of the Address Bus proportional to?

A
  • The number of addressable memory locations
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18
Q

What is the Control Bus?

A
  • Bi-directional bus used to transmit Control Signals between internal and external components
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19
Q

What does the Control Bus do?

A
  • Coordinates the use of Address and Data Busses
  • Provides status information between system components
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20
Q

What does the Control Signal ‘Bus Request’ do?

A
  • Shows that a device is requesting the use of the Data Bus
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21
Q

What does the Control Signal ‘Bus Grant’ do?

A
  • Shows that the CPU has granted access to the Data Bus
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22
Q

What does the Control Signal ‘Memory Write’ do?

A
  • Data is written into the addressed location using this bus
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23
Q

What does the Control Signal ‘Memory Read’ do?

A
  • Data is read from a specific location to be placed onto the Data Bus
24
Q

What does the Control Signal ‘Interrupt Request’ do?

A
  • Shows that a device is requesting access to the CPU
25
Q

What is the Clock used for?

A
  • To synchronise operations
26
Q

What is the Fetch-Decode-Execute cycle?

A
  • A sequence of operations completed in order to execute an instruction
27
Q

What happens in the registers during the first part of the ‘Fetch’ stage of the FDE cycle?

A
  • Address from PC is copied to the MAR
28
Q

What happens in the registers during the second part of the ‘Fetch’ stage of the FDE cycle?

A
  • Instruction held at the address is copied to MDR by the Data Bus
  • Simultaneously, the contents of the PC are increased by 1
29
Q

What happens in the registers during the third part of the ‘Fetch’ stage of the FDE cycle?

A
  • The value held in the MDR is copied to the CIR
30
Q

What happens in the registers during the ‘Decode’ stage of the FDE cycle?

A
  • The contents of the CIR are split into operand and opcode
31
Q

What happens in the registers during the ‘Execute’ stage of the FDE cycle?

A
  • The decoded instruction is executed
32
Q

What is the System Clock?

A
  • An electronic device that generates signals, switching between 0 and 1
33
Q

What is Clock Speed?

A
  • The time taken for one clock cycle to complete
34
Q

What is a Core?

A
  • An independent processor that is able to run its own FDE cycle
  • A computer with multiple cores can complete more than one FDE at any given time
35
Q

What programs can utilise multiple Cores?

A
  • Not all programs are able to utilise multiple cores efficiently as they have not been designed to do so
  • Executing tasks faster may not always be possible
36
Q

What is Level 1 Cache?

A
  • Very fast memory cells with a small capacity (2 - 64KB)
37
Q

What is Level 2 Cache?

A
  • Relatively fast memory cells with a medium sized capacity (256KB - 2MB)
38
Q

What is Level 3 Cache?

A
  • Much larger and slower memory cell
39
Q

What is Pipelining?

A
  • The process of completing FDE cycles of three separate instructions simultaneously, holding appropriate data in a buffer in close proximity to the CPU until it’s required
40
Q

What is the purpose of Pipelining?

A
  • Aimed to reduce the amount of CPU which is kept idle
41
Q

What is Instruction Pipelining?

A
  • Separating out the instruction into Fetching, Decoding, and Executing
42
Q

What is Arithmetic Pipelining?

A
  • Breaking down the arithmetic operations and overlapping them as they are performed
43
Q

What does Von Neumann Architecture include?

A
  • Basic components of the computer and processor:
  • Single CPU
  • ALU
  • Registers
  • Memory Units
44
Q

What concept is Von Neumann Architecture built upon?

A
  • The stored program concept
45
Q

What Buses are used in Von Neumann Architecture?

A
  • A shared Memory and Data Bus is used for both Data and Instructions
46
Q

What is the main feature of Harvard Architecture?

A
  • Physically separate memories for Instructions and Data
47
Q

What is Harvard Architecture commonly used with?

A
  • Embedded processors
48
Q

When is it useful to utilise Harvard Architecture?

A
  • When Memories have different characteristics
  • i.e. Instructions may be read only, while Data may be read-write
49
Q

What does Harvard Architecture allow for?

A
  • The optimisation of the size of individual memory cells and their Buses depending on needs
  • i.e. The Instruction Memory can be designed to be larger so a larger word size can be used for Instructions
50
Q

What is the first advantage of Von Neumann Architecture?

A
  • Cheaper to develop as the CU is easier to design
51
Q

What is the second advantage of Von Neumann Architecture?

A
  • Programs can be optimised in size
52
Q

What is the first advantage of Harvard Architecture?

A
  • Quicker execution as Data and Instructions can be fetched in parallel
53
Q

What is the second advantage of Harvard Architecture?

A
  • Memories can be different sizes, which can make more efficient use of space
54
Q

What is Contemporary Architecture (Contemporary Processing)?

A
  • The use of a combination of Von Neumann and Harvard Architecture
55
Q

When is Von Neumann Architecture used in Contemporary Architecture (Contemporary Processing)?

A
  • When working with Data and Instructions in main memory
56
Q

What is Harvard Architecture used for in Contemporary Architecture (Contemporary Processing)?

A
  • To divide the Cache into Instruction Cache and Data Cache

Computer Science 1.1 - Components of a Computer (3 decks)

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