1.1.1 - Structure And Function of the Processor

Question 1

Central Processing Unit (CPU)

Answer 1

• Are general purpose processors that execute instructions in a computer system through the fetch-decode-execute (FDE) cycle.
• Each consists of: An Arithmetic Logic Unit (ALU), A Control Unit (CU), Registers and Buses.

Question 2

Arithmetic Logic Unit (ALU)

Answer 2

• Carries out arithmetic calculations and logical decisions.
• The results of its calculations are stored in the Accumulator (ACC).

Question 3

Control Unit (CU)

Answer 3

• Decodes instructions
• Manages the execution of instructions using control signals to coordinate movement of data through the processor and other parts of the computer.
• Controls buses

Question 4

Register

Answer 4

• Small piece of memory used for storing data within the processor
• They provide faster access to data than RAM for specific purposes during FDE cycle when frequent access is needed.

Question 5

Program Counter (PC)

Answer 5

– Stores the address of the next instruction to be processed
– Value is then sent to the MAR
– After sending the value the PC is incremented / changed to address held in CIR if the operation is a Jump

Question 6

Accumulator (ACC)

Answer 6

• Temporary storage for data being processed / during calculations
• Deals with the I/O data in the processor and is used as a buffer

Question 7

General Purpose Register (GPR)

Answer 7

Used to temporarily store data being used rather than sending data to and from the comparatively much slower memory.

Question 8

Memory Address Register (MAR)

Answer 8

Contains the address of the next location to be accessed in memory copied from the PC

Question 9

Memory Data Register (MDR)

Answer 9

Contains the data which has been accessed from the memory location referenced by the MAR when being transferred to the CIR

Question 10

Current Instruction Register (CIR)

Answer 10

Holds the most recently fetched data/instructions to be decoded and executes into opcode and operand.

Question 11

Bus

Answer 11

A parallel group of communication channel wires able to transmit data in groups of bits together from one register to another.

Question 12

Data Bus

Answer 12

Carries the data being transmitted from one register to another.

Question 13

Address Bus

Answer 13

Carries the memory location address of the register where the data is being transmitted to or from.

Question 14

Control Bus

Answer 14

Transmits control signals from the CU to allow synchronisation of signals to the rest of the processor.

Question 15

Fetch - FDE Cycle

Answer 15

• Data/address is copied from the PC to the MAR
• PC is incremented by 1 in each cycle
• Read signal is sent on the control bus.
• RAM copies the data from the location specified by the address bus onto the data bus.
• Data on the data bus is passed into the MDR
• Data is copied from the MDR to the CIR

Question 16

Decode - FDE Cycle

Answer 16

• Load instruction from address in MAR pointed to MDR.
• The instruction is copied from MDR to CIR.
• The instruction is decoded into opcode and operand by the CU in the CIR.

Question 17

Execute - FDE Cycle

Answer 17

The appropriate instruction opcode is carried out on the operand by the processor.

Question 18

Clock Speed

Answer 18

• Number of instruction cycles per second a CPU can execute
• Measured in Hz (1 GHz = 1 billion instructions per second)

Question 19

Effect of increased Clock Speed

Answer 19

• Gives more cycles per second so more instructions can be executed per second
• So the program takes less time to run

Question 20

Number of Cores

Answer 20

• Each core is a distinct processing unit on the CPU; each with their own Registers, ALU, Accumulator, CU etc.
• Processors can have multiple cores to speed up smaller problems or when multitasking, different cores can run different applications/programs at the same time.

Question 21

Cache

Answer 21

• Small storage of data and instructions that are likely to be regularly accessed

Question 22

Effect of increased Cache Size

Answer 22

• More space for data / instructions in cache memory so RAM needs to be accessed less
  frequently
• Saves time as accessing cache is quicker than accessing the RAM

Question 23

Pipelining

Answer 23

• Would allow one instruction to be fetched as the previous one is being decoded and the one before that is being executed.
• Jump instructions do not pipeline well as they could be followed by one of many instructions determined at execution, so the wrong one may be fetched/decoded

Question 24

Von Neumann Architecture

Answer 24

• Uses shared memory space for instructions and data; these are stored in the same format.
• Single set of buses
• A single CU and processor uses FDE cycle to execute one instruction at a time in a linear sequence.
• Simple OS and easy to program but slow processing large sets of data.

Question 25

Harvard Architecture

Answer 25

• Data/instructions are stored with fixed memory sizes in separate memory units with separate buses.
• So while data is being written to or read from the data memory, the next instruction can be read from the instruction memory.
• Used by RISC processors

Question 26

Contemporary Processor Architecture

Answer 26

Modern high-performance CPU chips that incorporate aspects of both architectures.

Question 27

Why can Pipelining improve the performance of a processor?

Answer 27

• Reduces/removes latency
• CPU is not idle while waiting for next instruction
• Next instruction is fetched while current one is decoded/executed
• All parts of the processor can be used at any instance in time.