1.1.1 Structure and function of the processor

Question 1

Purpose of the ALU?

Answer 1

● The ALU (Arithmetic and Logic Unit) completes the arithmetical and logical operations .

Question 2

Purpose of the Control Unit?

Answer 2

● The Control Unit is the component of the processor which directs operations inside the CPU . It has the following jobs:
○ Controlling and coordinating the activities of the CPU
○ Managing the flow of data between the CPU and other devices
○ Accepting the next instruction
○ Decoding instructions
○ Storing the result back in memory

Question 3

What are registers?

Answer 3

● Registers are small memory cells that operate at very high speeds,
● They are used to temporarily store data,
● All arithmetic, logical or shift operations occur in these registers

Question 4

Purpose of the Program Counter?

Answer 4

• Holds the address of the next instruction to be executed

Question 5

Purpose of Accumulator?

Answer 5

• Stores the results from calculations

Question 6

Purpose of Memory Address Register (MAR)?

Answer 6

• Holds the address of a location that is to be read from or written to .

Question 7

Purpose of Memory Data Register (MDR)?

Answer 7

• Temporarily stores data that has been read or data that needs to be written .

Question 8

Purpose of Current Instruction Register (CIR)?

Answer 8

• Holds the current instruction being executed, divided up into operand and opcode.

Question 9

What are Buses?

Answer 9

● Buses are a set of parallel wires which connect two or more components inside the CPU together
● The collection of the data bus, control bus, and address bus is called the system bus
● The width of the bus is the number of parallel wires the bus has.

Question 10

What is the Data Bus?

Answer 10

● This is a bi-directional bus (meaning bits can be carried in both directions) used for transporting data and instructions between components.

Question 11

What is the Address Bus?

Answer 11

● Used to transmit the memory addresses specifying where data is to be sent to or retrieved from
● Adding a wire to the address bus doubles the number of addressable locations

Question 12

What is a Control Bus?

Answer 12

● This is a bi-directional bus used to transmit control signals between internal and external components.

Question 13

What are the control signals?

Answer 13

○ Bus request: shows that a device is requesting the use of the data bus
○ Bus grant: shows that the CPU has granted access to the data bus
○ Memory write: data is written into the addressed location using this bus
○ Memory read: data is read from a specific location to then be placed onto the data bus
○ Interrupt request: shows that a device is requesting access to the CPU
○ Clock: used to synchronise operations

Question 14

Explain the relationship of opcode with assembly language?

Answer 14

● Assembly code uses mnemonics to represent instructions.
● It is a simplified way of representing machine code .
● The instruction is divided up into operand and opcode
● Opcode is used to determine the type of instruction and what hardware to use to execute it.
● The operand is the address of where the operation is performed.

Question 15

What is the fetch-decode-execute cycle?

Answer 15

• The sequence of operations that are completed in order to execute an instruction.

Question 16

What happens in the Fetch Phase?

Answer 16

• Address from the PC is copied to the MAR,
• Instruction held at that address is copied to MDR by the data bus, simultaneously the contents of the PC are increased by 1,
• The value held in the MDR is copied to the CIR.

Question 17

What happens in the Decode Phase?

Answer 17

• The contents of CIR are split into operand and opcode

Question 18

What happens in the execute Phase?

Answer 18

• The opcode is executed on the operand.

Question 19

What are the factors affecting CPU performance?

Answer 19

• Clock speed* Number of cores* Amount and type of Cache Memory

Question 20

How does Clock speed effect the CPU?

Answer 20

● Clock speed is determined by the system clock
● All processor activities begin on a clock pulse
● Each CPU operation starts as the clock changes from 0 to 1
● The clock speed is the number of clock cycles completed in a second.

Question 21

How do the number of cores effect the CPU?

Answer 21

● A core is an independent processor that is able to execute its own fetch-execute cycle
● A computer with multiple cores can complete more than one fetch-execute cycle at any given time
● Some programs aren’t optimised for the use of more than one core.

Question 22

How does cache memory effect the CPU?

Answer 22

● Cache memory is the CPU’s onboard memory
● Instructions fetched from main memory are copied to the cache, so if required again it can be accessed quicker.
● As cache fills up, unused instructions get replaced.

Question 23

What are the types of cache memory?

Answer 23

Level 1 Cache: Very fast memory cell, however it also has a small amount of capacity. (2-64KB)
Level 2 Cache: Relatively fast memory cell, with medium sized capacity. (256KB-2MB)
Level 3 Cache: Slower memory cell, however it has a much larger capacity.

Question 24

What is pipelining?

Answer 24

● Pipelining: The process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously
● Data is held in a buffer in close proximity to the CPU until it’s required
● Pipelining is aimed to reduce the amount of the CPU which is kept idle .

Question 25

What is the Von Neumann Architecture?

Answer 25

● Von Neumann includes a single control unit , ALU , registers and memory units
● Shared memory and data bus used for both data and instructions.

Question 26

Describe the Harvard Architecture

Answer 26

● Physically separate memories for instructions and data
● More commonly used with embedded processors

Question 27

What are the advantages of Von Neumann Architecture

Answer 27

• Cheaper to develop since the control unit is easier to design.
• Programs can be optimised in size .

Question 28

What are the advantages of Harvard Architecture?

Answer 28

• Quicker since data and instructions can be fetched in parallel.
• Both memories can be different sizes

Question 29

What is contemperary processing?

Answer 29

● The combination of Harvard and Von Neumann architecture
● Uses Von Neumann when working with the data and instructions in main memory
● Uses Harvard when working with cache.
● There is an instruction cache and data cache.