1.1.1 structure and function of the CPU

Question 1

What does the ALU do?

Answer 1

Completes all arithmetic and logical operations
ADD/SUB etc..
AND, OR, NOT…

Question 2

Purpose of the CU?

Answer 2

Directs the operations of the CPU
* Controls and coordinated CPU activities
* Manages flow of data between CPU and other devices
* Accepts the next instruction
* Decodes instructions
* Stores resulting data back in memory

Question 3

What is the purpose of the PC

register

Answer 3

Holds address of the next instruction to be executed

Question 4

Purpose of the ACC

Answer 4

Stores results of calculations (performed by the ALU)

Question 5

Purpose of the MAR

Answer 5

Holds the address of a location that data is to be read from or written to

Question 6

Purpose of the MDR

Answer 6

Temporarily stores data that has been read or needs to be written

Question 7

Purpose of the CIR

Answer 7

Holds the current instruction being executed, divided up into operand and opcode

Question 8

What is the data bus?

Answer 8

Bi-directional bus used for transporting data and instructions between components

Question 9

What is the address bus?

Answer 9

Transmits the memory addresses specifying where data is to be sent to or retrieved from

Question 10

What is the control bus?

Answer 10

Bi-directional bus used to transmit control signals between internal and external components
* Bus requests
* Bus grant
* Memory write
* Memory read
* Interrupt request

Question 11

What are opcode and operand?

Answer 11

-Opcode: Specifies the type of instruction to be executed
-Operand: Address of the data upon which the operation is to be performed

Question 12

What is pipelining?

Answer 12

-Completing the FDE cycles of 3 instructions simultaneously
-Reduces the amount of the CPU kept idle
-Can be arithmetic or instruction

Question 14

What does the fetch stage of the FDE do

Answer 14

1. PC is loaded with 0
2. Value from the PC is copied to the MAR
3. Data from the MAR is sent across the address bus with the instruction to read the data send across the control bus
4. Data from that location in memory is sent down the data bus to the MDR
5. PC incremented by 1

Question 15

What happens in the decode stage?

Answer 15

1. The data is sent from the MDR to the CIR where it is split into opcode and operand
2. This is sent to the CU to be decoded

Question 16

What happens in the execute stage?

Answer 16

Depends on the instruction being executed:
* If a value is inputted the ACC stores the value
* If outputted, it is the value currently in the ACC
* If a value is loaded from RAM it is sent across the data bus to the MDR
* If it is to be stored it will take the value ftom the ACC, send it to the MDR then across the data bus to RAM
* If branching the comparison will take place in the ALU

Question 17

Factors affecting CPU performance

Answer 17

• Clock speed- time taken for one clock cycle to complete, Hz
• Number of cores- Independent processor able to do its own FDE cycle. More cores = more FDE cycles at a given time (not all programs able to utilise multiple cores)
• Cache- memory in the CPU’s onboard memory. Accessed faster than main memory.
  Level 1 cache- very fast, small capacity (2-64KB)
  Level 2 cache- Relatively fast, medium capacity (256KB-2MB)
  Level 3- Much larger and slower

Question 18

Von Neumann architecture

Answer 18

-Single CU, ALU, registers and memory units
-Shared memory and shared data bus used for both data and instructions
*Cheap to develop as CU easier to design
*Programs can be optimised in size

Question 19

Hardvard architecture

Answer 19

Seperate memory spaces for data and instructions. Commonly used with embedded processors
*Quicker execution as data and instructions can be fetched in parallel
*Memories can be different sizes