1.1.1: Structure and Function of Processor

Question 1

processor

Answer 1

“brain of the computer”, executes instructions. allowing programs to run

Question 2

FDE Cycle

Answer 2

Fetch

• address from PC copied to MAR
• instruction held at address copied to MDR by data bus
• simultaneously, contents of PC increased by 1
• value of MDR copied to CIR

Decode

• contents of CIR split into operand and opcode

Execute

• decoded instruction is executed

Question 3

Registers

Answer 3

small memory cells that operate at high speed. Temporary storage

Question 4

Program Counter (PC)

Answer 4

holds address of next instruction to be executed

Question 5

Accumulator (ACC)

Answer 5

stores result from calculations

Question 6

Memory Address Register (MAR)

Answer 6

holds address of location that is to be read from/written to

Question 7

Memory Data Register (MDR)

Answer 7

temporarily stores data that has been read/data that needs to be written

Question 8

Current Instruction Register (CIR)

Answer 8

holds current instruction being executed. Divides up into operand and opcode

Question 9

Arithmetic Logic Unit (ALU)

Answer 9

completes all arithmetical (mathematical) and logical (boolean- AND, OR, NOT, XOR) operations

Question 10

Control Unit (CU)

Answer 10

• Directs operations of CPU
• controls and coordinates activities of CPU
• manages the flow of data (CPU to other devices)
• monitors FDE cycles

Question 11

Buses

Answer 11

set of parallel wires connecting 2 or more components in the CPU

Question 12

Data bus

Answer 12

A bi-directional bus for carrying data and instructions between the processor and memory.

Question 13

Address bus

Answer 13

transmit memory addresses specifying where data is being sent/retrieved

Question 14

Control Bus

Answer 14

This bus carries command and control signals to and from every other component of a computer.

Question 15

Control bus signals….

Answer 15

• Bus request
• Bus grant
• Memory write
• Memory read
• Interrupt request
• Clock

Question 16

Factors affecting CPU: Clock Speed

Answer 16

• determined by system clock
• clock generates signals switching between 0 and 1
• Time taken for 1 clock cycle

Question 16

Factors affecting CPU: Number of Cores

Answer 16

• Core = independent processor able to run its own FDE cycle
• multiple cores = able to complete more than 1 FDE cycle
• Dual cores = theoretically complete task 2x faster but not all computer programs can utilise multiple core efficiently

Question 16

Assembly Language

Answer 16

Assembly code uses mnemonics to represent instruction, ADD = +

• Instructions are divided into operand an copcode in CIR
• Operands holds data/ address of dataof which operation is to be performed
• Opcode specifies type of instruction to be executed

Question 17

Factors affecting CPU: Amount of cache

Answer 17

• Cache = CPU’s onboard memory
• instructions fetched from main memory copied to cache –> able to be accessed quickly and unused instructions are replaced

Question 18

Levels of Cache

Answer 18

LVL 1: very fast memory cells with small capcity (2-64KB)

LVL 2: Fairly fast, medium sized capacity (256KB - 2MB)

LVL 3: Much larger and slower

Question 19

Von Neumann

Answer 19

• basic components of computer + processor (CU, ALU, registers, memory units)
• Shared memory + shared data bus is used for instructions + data
• Built on stored program concept

Question 20

Harvard

Answer 20

• physically separate memories for instructions + data
• used more commonly in embedded systems
• useful when memories have different characteristics: instructions = read-only, data = read-write
• allow you to optimise size of individual memory cells + buses depending on needs

Question 21

Advantages of Von Neumann

Answer 21

• cheaper to develop - CU is easy to design
• program can be optimised in size

Question 22

Advantages of Harvard

Answer 22

• quicker execution - data + instructions fetched in parallel
• memories can be different sizes - more efficient use of space

Question 23

Contemporary processing

Answer 23

• uses both VN and H architecture
• VN = working with data and instructions in main memory
• H = divide cache into instruction cache + data cache