1.1.1: Structure and Function of Processor Flashcards
processor
“brain of the computer”, executes instructions. allowing programs to run
FDE Cycle
Fetch
- address from PC copied to MAR
- instruction held at address copied to MDR by data bus
- simultaneously, contents of PC increased by 1
- value of MDR copied to CIR
Decode
- contents of CIR split into operand and opcode
Execute
- decoded instruction is executed
Registers
small memory cells that operate at high speed. Temporary storage
Program Counter (PC)
holds address of next instruction to be executed
Accumulator (ACC)
stores result from calculations
Memory Address Register (MAR)
holds address of location that is to be read from/written to
Memory Data Register (MDR)
temporarily stores data that has been read/data that needs to be written
Current Instruction Register (CIR)
holds current instruction being executed. Divides up into operand and opcode
Arithmetic Logic Unit (ALU)
completes all arithmetical (mathematical) and logical (boolean- AND, OR, NOT, XOR) operations
Control Unit (CU)
- Directs operations of CPU
- controls and coordinates activities of CPU
- manages the flow of data (CPU to other devices)
- monitors FDE cycles
Buses
set of parallel wires connecting 2 or more components in the CPU
Data bus
A bi-directional bus for carrying data and instructions between the processor and memory.
Address bus
transmit memory addresses specifying where data is being sent/retrieved
Control Bus
This bus carries command and control signals to and from every other component of a computer.
Control bus signals….
- Bus request
- Bus grant
- Memory write
- Memory read
- Interrupt request
- Clock
Factors affecting CPU: Clock Speed
- determined by system clock
- clock generates signals switching between 0 and 1
- Time taken for 1 clock cycle
Factors affecting CPU: Number of Cores
- Core = independent processor able to run its own FDE cycle
- multiple cores = able to complete more than 1 FDE cycle
- Dual cores = theoretically complete task 2x faster but not all computer programs can utilise multiple core efficiently
Assembly Language
Assembly code uses mnemonics to represent instruction, ADD = +
- Instructions are divided into operand an copcode in CIR
- Operands holds data/ address of dataof which operation is to be performed
- Opcode specifies type of instruction to be executed
Factors affecting CPU: Amount of cache
- Cache = CPU’s onboard memory
- instructions fetched from main memory copied to cache –> able to be accessed quickly and unused instructions are replaced
Levels of Cache
LVL 1: very fast memory cells with small capcity (2-64KB)
LVL 2: Fairly fast, medium sized capacity (256KB - 2MB)
LVL 3: Much larger and slower
Von Neumann
- basic components of computer + processor (CU, ALU, registers, memory units)
- Shared memory + shared data bus is used for instructions + data
- Built on stored program concept
Harvard
- physically separate memories for instructions + data
- used more commonly in embedded systems
- useful when memories have different characteristics: instructions = read-only, data = read-write
- allow you to optimise size of individual memory cells + buses depending on needs
Advantages of Von Neumann
- cheaper to develop - CU is easy to design
- program can be optimised in size
Advantages of Harvard
- quicker execution - data + instructions fetched in parallel
- memories can be different sizes - more efficient use of space
Contemporary processing
- uses both VN and H architecture
- VN = working with data and instructions in main memory
- H = divide cache into instruction cache + data cache
