1.1.1 Processor Architecture Flashcards
What is a computer system
The hardware and software that work together to process inputs with instructions and produce an output
Hardware - physical components
software - programs that make hardware do useful things
Peripherals - hardware connected to computer
Control unit
Central component of CPU
- Co-ordinates activity of CPU with other components
- Decodes instructions
- Controls buses - sends control signals to co-ordinate movement of data through processor with other devices
- Controls buses - manages FDE cycle
Function and Components of CPU
CPU processes instructions and data through the fetch decode execute cycle
-Control unit
-Arithmetic-Logic unit
-Dedicated registers
-Cache
-Buses
ALU and Registers
Arithmetic Logic unit
- Does calculations (Arithmetic and Logical operations)
Registers
- Small memory located in the CPU
- Very fast access speed
- Temporary store of data
- Dedicated purpose - single specific purpose
All Registers
Accumulator :
- Temporary storage for data being processed during calculations (result of ALU)
- Used as input / output - buffer / gateway
Program Counter :
- Holds memory location of next instruction to be fetched
- Increments by one every FDE cycle
- Keeps track of where in memory currently at
Memory address register :
- Holds memory address of instruction currently being fetched from or sent to
Memory data register :
- Temporarily stores data that has been read from memory or to be written to memory
Current instruction register :
- Stores the current instruction being executed (most recently fetched)
Buses
Set of parallel wires that connect two or more components - series of connectors that transfer signals between internal components
Data Bus : Bi-directional and carries data from one component to another
Address Bus : Carries memory address of where data is to be written to or read from
Control Bus : Bi-directional and used to transmit control signals (read or write from memory/ clock to synchronize operations)
Factors affecting CPU performance
Clock speed - Speed a FDE cycle is completed - number of instructions that can be executed per second increases so programs can be executed faster in less time.
Cache size - Memory that contains frequently used instructions/data and has a faster R/W speed than RAM because it is located nearer to the CPU than RAM - more cache means more data can be stored which speeds up CPU performance.
Number of Cores - Independent processing units that can complete more than one FDE cycle at the same time through parallel processing and splitting a task between cores to reduce time to process.
FDE cycle (read)
- Contents of PC copied to MAR (Fetch)
- PC increments by one
- Memory address sent down address bus from MAR
- Control bus sends read signal to RAM
- Data from memory location referenced by MAR sent down data bus to MDR
- Data copied to CIR from MAR and split into opcode and operand (Decode)
- Data Decoded by CU
- Data executed and placed in accumulator (execute)
FDE cycle (Write)
(after fetching and decoding instruction to write into memory) so this is execute stage :
- Contents of CIR (address) copied to MAR
- Memory address sent down address bus from MAR
- Control bus sends write signal to RAM
- Accumulator data copied to MDR and Data sent down data bus from MDR to memory location in RAM.
Von Neumann architecture
Von Neumann
- Shared memory location unit/block for data and instructions
- Data and instructions stored in same format
- Single CU follows linear FDE cycle
- Single set of buses for data and instructions
- Used in most modern computers
ADV:
- Simpler design for CU so cheaper to develop
- Backwards compatible as data accessed from memory in same way
DISADV:
- Single bus causes bottleneck which reduces speed of execution of programs.
Harvard architecture
Harvard :
- Separate memory location units/blocks for data and instructions.
- Each memory unit has own buses.
- Separate control units
- Speed priority over complexity.
Common in embedded processors as :
- instructions fixed size,
- no need for instructions to be changed,
- no need for memory to be shared between data and instructions.
ADV:
- Quicker execution and efficiency - data and instructions can be fetched concurrently as two sets of buses.
DISADV:
- Increased complexity of design
- Data and instructions stored in different formats - compatibility issues
Contemporary architectures
Make use of many features that make the processor more efficient such as :
Two separate areas of memory…
…one for instructions & one for
data./instructions and data can be
accessed concurrently.
Different (sets of) buses…
… one for instructions & one for data./
instructions and data can be accessed
concurrently.
Pipelining…
…whilst an instruction is being executed
the next can be decoded and the
subsequent one fetched.
Use of Cache…
…A small amount of high performance
memory is (next to the CPU) / which stores frequently used data/instructions
Virtual cores/Hyper-threading …
…Treating a physical core as two virtual cores.
Multiple Cores…
…Each core acts as a separate
processing unit.
Onboard Graphics…
…Built in circuitry for graphics processing
Pipelining - CPU
Pipelining : Concurrent processing of multiple instructions
While one instruction is being decoded the next one is being fetched and previous one is being executed - completing FDE cycle of 3 separate instructions simultaneously.
(Output of process becomes input for next process)
ADV:
- More instructions carried out in set amount of time (instructions not faster)
- Increases efficiency and speed of execution of programs
- CPU is not idle waiting for next instruction so reduces latency (time for multiple instructions to go through FDE cycle)
- All parts of processor used at any instance of time - register values not idle
DISADV:
- When branching the next instruction to be processed is no longer the next in memory - so must flush the pipeline
