1.1.1 Flashcards

1
Q

What is the CIR and what is its purpose?

A

Current Instruction Register (CIR) - Holds the instruction while it is being decoded/executed.

Contents are split into opcode and operand

operand is copied to MAR if it is an address or MDR if it is data

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2
Q

What is the MDR and what is its purpose?

A

Memory Data Register (MDR) - Contains the instruction or data which has been accessed from memory

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3
Q

What is the MAR and what is its purpose?

A

Memory Address Register (MAR) - Contents of the PC are copied here in order for the processor to access the next instruction

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4
Q

What is the ACC and what is its purpose?

A

Accumulator (ACC) - Temporary storage for data being processed (input and output) - Holds results of calculations (from the ALU)

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5
Q

What is the PC and what is its purpose?

A

Program Counter (PC) - Stores the address of the next instruction to be fetched

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6
Q

What is the CU and what is its purpose?

A

Control Unit (CU) – Decodes instructions and sends out control signals

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7
Q

What is the purpose of the address bus?

A

Address Bus – Carries the address where the data is going to or from

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8
Q

What is the ALU and what is its purpose?

A

The Arithmetic and Logic Unit (ALU) - Carries out calculations and logical instructions

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9
Q

What is the purpose of the data bus?

A

Data Bus - Carries the data from one place to another

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10
Q

What is a register?

A

Register - Small piece of temporary memory located within the processor/CPU. Used for a specific purpose.

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11
Q

What is the purpose of the control bus? What CPU component would use this bus?

A

Control Bus - Carries control signals from the control unit to other parts of the system

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12
Q

What are the sub-stages of the fetch part of the FDE cycle?

A
  1. Data/address is copied from PC to MAR
  2. PC is incremented (usually by 1)
  3. Data in MAR is passed onto the Address Bus
  4. Read signal is sent onto the control bus
  5. RAM copies the data from the location specified by the address bus onto the data bus
  6. Data on the data bus is passed into the MDR
  7. Data is copied from the MDR to the CIR
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13
Q

What are some key facts about the Von Neumann Processor

A

Data and Instructions are stored in the same area of memory in the same format
Uses the same bus for data and instructions - can only fetch either data or instructions at one time

Single CU / ALU
Uses the special registers (MDR, ACC etc..)
Follows the Fetch Decode Execute cycle

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14
Q

What are some key facts about the Harvard Processor

A
  • Separate memory for instructions and data
  • Has separate data and address buses for instructions
  • Instructions and data can be retrieved in parallel
  • Has fixed memory sizes for data and Instructions
  • Instruction memory may be ROM
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15
Q

What is a contemporary architecture and what features may it have?

A

AKA - Modern Processors - Has aspects of both Von Neumann and Harvard.

Have features such as:

  • Pipelining
  • Make use of cache
  • Virtual Cores
  • Hyper Threading
  • Multiple Cores
  • On-board Graphics
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16
Q

What are the recognised factors affecting the performance of a CPU?

A
  1. Clock Speed
  2. Number of Cores
  3. Cache Size/Speed
17
Q

How does the clock speed influence the performance of the CPU?

A

The speed at which the fetch decode execute cycle is completed. Higher clock speed gives more cycles per second meaning more instructions can be executed per second (program takes less time to run)

18
Q

How does the number of cores influence the performance of the CPU?

A

Each core is a processing unit, giving the potential for multiple instructions to be run at the same time

19
Q

How does the cache size influence the performance of the CPU?

A

High levels of cache give more space for data/instructions so slower RAM needs to be accessed less frequently.

20
Q

What is pipelining?

A

Concurrent processing of multiple instructions – increases speed of the program

Would allow one instruction to be fetched as the previous one is being decoded and the one before that is being executed.

21
Q

What issues does pipeling face?

A

Struggles with code that uses branching, as wrong instruction may be brought, meaning flush would be used.