1.1 Processor Components Flashcards
Control Unit
The part of the CPU that coordinates the activity of all other components
What are control signals?
Signals that are sent along the control bus between the control unit and the other components of the computer
What is a bus?
Consist of a series of connectors that transfer signals between internal components
System bus
Consists of three separate buses carrying control signals, addresses and data
List some control signals:
- Memory Read
- Memory write
- Bus request
- Bus grants
- Clock
Memory Read
Causes data from the addressed location in RAM to be placed on the data bus
Memory write
Causes data on the data bus to be written into the addressed location in RAM
Bus Request
Indicates that a device is requesting use of the data bus
Bus grant
Indicates that the CPU has granted access to the data bus
Clock
Used to synchronise operations
What does the ALU do?
- Component performs arithmetic, logical and shift operations on data
- Arithmetic operations, Add, Subtract, Multiply and Divide
- Logical operations: AND, OR, NOT, XOR
- Shift operations: Move bits to the left or right within a register
Accumulator
A general purpose register used to store the outputs of the ALU
Give the different dedicated registers
- Program Counter
- Current Instruction Register
- Memory Address Register
- Memory Data Register
- Accumulator
Fetch-execute cycle
Processors operate in defined stages that are used to cary out program instructions
Program Counter
Holds the memory address of the next instruction to be executed
Current Instruction Register
Holds the current instruction, which is split into opcode and operand
Memory Address Register
Holds the address in memory where the processor is required to fetch or store data from or to
Memory Data Register
Temporarily holds data moving between the processor and main memory
Accumulator
To hold intermediate results of an instruction
Fetch step 1
Address of next instruction transferred from PC to MAR
Fetch Step 2
Instruction stored in location addressed by MAR is transferred to MDR
Fetch Step 3
PC incremented by 1
Fetch Step 4
Instruction transferred from MDR to CIR
Decode step 5
Instruction held in the CIR is decoded
Decode step 6
It is split into operand and opcode to determine the type of instruction it is. Additional data (if required) is fetched from memory
Decode step 7
Gets passed to the accumulator
- The opcode specifies the operation that is to be carried out
- The operand holds either the address of the data to be used, which is then copied to the MAR or the actual data to be operated on which is passed to the MDR.
