1. 1. 1 Structure and Function of the Processor Flashcards
1
Q
Components of a Processor
A
- Processor is the brain of the computer; it executes instructions which allows programs to run
- The components of a processor are the ALU, CU, ACC, Registers, Buses and the 3 C’s
2
Q
Arithmetic and Logic Unit (ALU)
A
- Completes arithmetical and logical operations
- Arithmetical includes mathematical operations (Addition, Subtraction etc)
- Logical includes Boolean operations (AND, OR, NOT, XOR etc)
3
Q
Control Unit (CU)
A
- Directs operations of the CPU
- Jobs it has includes the following
- Controls / coordinates activities of CPU
- Manages flow of data between CPU and other devices
- Accepts next instruction
- Decodes instructions
- Stores resulting data back in memory
4
Q
Registers
A
- Small memory cells that operate at very high speeds, have one purpose
- Used to temporarily store data
- All arithmetic, logical and shift operations occur in registers
- Includes the PC, ALU, MAR, MDR, CIR and ACC
- Program Counter (PC) holds address of next instruction to be fetched, increments by 1 after fetch
- Accumulator (ACC) stores results from calculations made by ALU, acts as buffer
- Memory Address Register (MAR) holds address of location that is to be read from or written to
- Memory Data Register (MDR) temporarily stores data that has been read or that needs to be written
- Current Instruction Register (CIR) holds current instruction being decoded and executed, divided into operand and opcode
5
Q
Buses
A
- A set of parallel wires which connect two or more components inside CPU
- Three types, control bus, data bus and address bus
- Width of bus is number of wires it has
- This is directly proportional to bits that can be transferred simultaneously at any given time
- Typically, 8, 16, 32 or 64 wires wide
6
Q
Control Bus
A
- Bi-directional bus
- Transmits control signals between internal and external components
- Coordinates use of address and data buses
- Provides status info between system components
7
Q
Data Bus
A
- Bi-directional bus
- Transports data and instructions between components
8
Q
Address Bus
A
- Transmits memory addresses (specifies where data is to be sent or retrieved from) from the CPU to RAM
- Single-directional, CPU to Bus, Bus to RAM, does not go other way
- Width of this bus proportional to number of addressable memory locations
9
Q
Control Signals
A
- Transmitted by control bus
- Bus request, device requesting use of data bus
- Bus grant, CPU granted access to data bus
- Memory write, data written in addressed location
- Memory read, data read from specific location to be placed onto data bus
- Interrupt request, device requesting access to CPU
- Clock, used to synchronise operations
10
Q
Fetch Decode Execute Cycles
A
- Sequence of operations that are completed in order to execute an instruction
- Fetch Phase, Address from PC copied to MAR, Instruction held at address copied to MDR by data bus
- PC incremented by 1, Value held at MDR copied to CIR
- Decode Phase, contents CIR split into operand (actual data or address of data which operation is to be performed upon) and opcode (type of instruction)
- Execute Phase- The decoded instruction is executed (operand carried out on opcode)
11
Q
Pipelining
A
- Process of fetching, decoding and executing three instructions simultaneously, holds appropriate data in buffer until it is required
- Aims to reduce amount of CPU kept idle, separated into instruction pipelining and arithmetic pipelining
- Instruction pipelining is separating out instruction into F, D and E
- Arithmetic pipelining is breaking down arithmetic operations, overlapping them as they are performed
12
Q
Factors affecting CPU performance (3 C’s)
A
- There are 3 factors, number of cores, clock speed and amount of cache
13
Q
Clock speed
A
- Clock speed determined by system clock
- Higher clock speed more instructions per second
14
Q
Core
A
- A core is an independent processor that can run its own fetch-execute cycle
- Multiple cores can complete multiple fetch-execute cycles at once
- Program must utilise all cores to gain the benefits
- A greater number of cores means more fetch-execute cycles at once
15
Q
Cache
A
- Cache is small but quick memory (CPUs onboard memory)
- Instructions fetched from RAM copied here, quickly accessible if needed again
- As it fills up, unused instructions are replaced
- Level 1 Cache (Very fast, small capacity)
- Level 2 Cache (Relatively fast, medium capacity)
- Level 3 Cache (Slower but larger capacity)
