X) Internal Components, Buses, System Architecture Flashcards

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1
Q

What is a bus?

A

A bus is a set of parallel wires that connect together components inside a computer in order to pass signals through.

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2
Q

The Control Bus

A

The control bus transports signals both ways between the Processor to the controllers.
The control bus ensures that the correct data reached the correct component at the right time. This involves the synchronisation of signals and the control of access to data and address buses.

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3
Q

Interrupts

A

An interrupt is a signal which is sent from either a device or a piece of software to the operating system.
The hierarchy of interrupts is where the interrupt handler priorities interruptions, placing them into a queue with the most important first.
Interrupts are useful because if they weren’t around, a user may have to wait a while for a given app as it is not given a higher priority for the CPU to run.

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4
Q

Data Bus

A

The data bus transfers data between the processor and memory, it also transfers data to and from the I/O controllers. The size of the data bus determines how much data can be transmitted in one pulse of the clock.
The data bus width is the same as the word length of the processor.
Word length- the number of bits transferred as a unit.

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5
Q

Address Bus

A

The address bus is used to specify the physical address in memory so the data bus can access that address.
The address bus only goes in one direction- from the processor to memory.
The size of the address bus is measured in bits and represents the amount of memory that is addressable.

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6
Q

Addressable Memory

A

Addressable memory is the concept that data and instructions are stored in memory using discrete addresses (an unsigned binary number).
Data is stored in a specific location and the CPU, using the address bus, controls what is stored in each location.
Each address is assigned 8 bits of data, like a dictionary (Address: Data).

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7
Q

Embedded systems

A

An embedded system is one where there is a computer that has a specific job within a machine.

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8
Q

Digital Signal Processing (DSP)

A

Digital Signal Processing is the process of manipulating different types of signals with the intention to produce analogue signals.
DSP is used where the computer is continually monitoring analogue signals and turns them into digital signals to feed into a wider system.
For example; Thermostat, you continually check the temperature (analogue signal), then turning it into a digital signal as you turn up/down the heat.

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9
Q

The CPU

A

The central processing unit carries out computation on data by following instructions in order to produce an output.
Buses inside the CPU connect groups of transistors, the transistors are used to control the flow of electrical pulses timed by the computer’s clock.
The speed of the CPU is measured in GHz.

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10
Q

Main memory

A

Main memory stores both data and programs which are currently used by the processor.

RAM- stores data and can be read to and written from.
This is temporary storage (volatile), with 8 chips each made up of millions of cells each containing its own unique address. Each cell contains either an instruction or some data.

ROM- stores data that can be read from, but not written to. ROM is non-volatile and so stores a certain amount of information including the set-up of the computer and the BIOS. It checks that all hardware devices are plugged in and it loads parts of the operating systmem.

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11
Q

Input/ Output Controllers

A

The I/O controllers are responsible for receiving and sending instructions to various input and output devices.

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12
Q

Harvard Architecture

A

In Harvard architecture, the instructions and data are stored in separate memory units each with a different bus connected to the CPU.
While data is being written to memory the next piece of data can be fetched.

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13
Q

Von Neumann Architecture

A

In Von Neumann architecture the instructions and data share the same memory space and are served by one set of buses.

  • The information and data are stored in the same format, so there is no difference between the two forms when u look at its binary format.
  • Follows a linear fetch, decode and execute cycle and processes one instruction at a time.
  • Registers are used as fast access to data because it is quicker to handle data in the CPU than working with it directly in memory.
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14
Q

Harvard vs Von Neumann

A

Harvard:

+ives:

  • Data is handled faster
  • Can access instructions and read/write simultaneously.
  • ives:
  • More costly
  • Must use separate buses for transferring data

Von Neumann:

+ives:

  • Cheaper in cost
  • Same physical memory address is used for instructions and data.
  • ives:
  • Two clock cycles required to execute an instruction
  • Can not simultaneously access instructions and read/write.
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15
Q

The Fetch-Execute Cycle

A

The fetch-execute cycle is the process carried out by the processor when running programs. Each instruction is fetched from memory, decoded and then executed.
Before this process can be carried out the program instructions must be translated into machine code and instructions must be loaded from secondary storage to main memory.

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16
Q

The Fetch Stage

A

When an instruction wants to be fetched from the main memory, the PC keeps the address for the next instruction being executed. The contents of the PC is then copied to the MAR which is connected to the address bus.
Once the address instruction is on the address bus, the CU instructs a memory read operation to allow the contents of the memory location to be transferred to the processor.
Simultaneously, the contents of the PC are incremented by one so that they point to the address of the next instruction.
The contents of the memory data register MDR are copied to the current instruction register CIR. This ensures that the current instruction is kept safe so that the MDR can be used during the execute stage.

17
Q

The Decode Stage

A

The control unit decodes the instruction that is kept in the current instruction register (CIR). The instruction is split into operand and opcode to determine what type of instruction needs to be carried out and figuring out and where these are kept in main memory.

18
Q

The Execute Stage

A

The instruction is executed, the exact sequence of operands depends on the type of instruction that is executed.

19
Q

The Control Unit (CU)

A

The control unit is a part of the processor which manages the execution of instructions.

20
Q

The Arithmetic Logic Unit (ALU)

A

The arithmetic logic unit is part of the processor which carries out mathematical functions.
The ALU uses logical operations such as OR, AND & NOT to carry out the appropriate process required.

21
Q

The Clock

A

The clock is a device that generates a signal used to synchronise the components of a computer.

22
Q

Registers (Status and Interrupt)

A

The status register keeps track of the various functions of the computer.
The interrupt register stores details of any signals that have been received by the processor from other components attached to it. It also stores details of incoming interupts.

23
Q

Register

Four registers used by the fetch-execute cycle

A
  • A register is a small section of temporary storage that is in the processor. It stores data and control instructions used in the fetch-execute cycle.
  • The Current Instruction Register (CIR) stores the instruction that is currently being executed.
  • The Program Counter (PC) stores the memory location of the next instruction that will be needed by the processor.
  • The Memory Data Register (MDR) holds the data that has just been read from or is about to be written to main memory.
  • The Memory Address Register (MAR) stores the memory location where data in the MDR is about to be written to.
24
Q

Machine Code

A

In machine code, an instruction holds an operation code (opcode) in the first 4 bits and the operand ( the address where the data is held) in the second 4 bits.

25
Q

Assembly Code

A

Assembly code uses mnemonics to represent operation code and addresses.
A typical assembly language comment:

LDR R1, 300

LDR- (Load Value) Opcode, the operation instruction.
R1 - Operand, a value or memory address
300- addressing mode, the way in which the operand is interpreted.

Adding comments; load contents of 300 into R1.

26
Q

Immediate and Direct Addressing

A

SUB R3, R2, #5
This instruction uses immediate addressing as it uses the actual value 5 as the operand.

LDR R1, 300
This instruction uses direct addressing as it uses the memory address (300) as the operand.

27
Q

Branch operations

A

Branch operations are operations within an instruction set that allows you to move from one part of a program to another.

28
Q

Example 1:

CMP r1, #10 
BNE else
MOV r2, #9
B endif
else
ADD r1, r1, #1
endif
A

CMP r1, #10 Compare the value stored in r1 to 10.
BNE else Branch if r1 != 10
MOV r2, #9 Move the value 9 into r2.
B endif
else
ADD r1, r1, #1 Add 1 to the value stored in r1.
endif

29
Q

Example 2:

MOV r1, #0
LOOP 
INPUT r0 
ADD r1, r1, r0 
CMP r0, #0
BNE LOOP
STR r1, 100
A

MOV r1, #0 Move the value 0 into r1, initialising to hold total.
LOOP
INPUT r0 Input a number
ADD r1, r1, r0 Add r0 to r1 and store the result as r1(total).
CMP r0, #0 Compare value 0 with r0.
BNE LOOP Branch if != 0
STR r1, 100 Store r1 (total) in location 100

30
Q

Logical Bitwise Operations
AND
OR
NOT

A

AND - used to mak out certain bits of a number, for example, it could be used to change an ASCII number to a binary number by masking the first 4 bits.
LDR R2, 201
AND R3, R2, #00001111B(B represents the binary value)

OR- used to set certain bits to 1 without affecting other bits, for example, 8 lights and only turning on the 7th and 8th light.
LDR R2, 200
ORR R3, R2, 00001111B
STR R3, 200

NOT- used to find the two's complement of a number. 
A = 0110 1100
NOT A = 1001 0011
ADD 1 = 0000 0001
= 1001 0100

MVN R1, #01101100B
ADD R1, R1, #1

31
Q

Logical Shift Operations

A

A logical shift to the right moves all bits as far as stated by the operand.

LSR R2, R1, #2
R1 = 10111100
R2= 00101111

A logical shift to the left moves all the bits as far as stated by the operand.

LSL R2, R1, #1
R1= 10111100
R2= 01111000