Week One Lectures Flashcards
Hardware refers to:
the tangible physical devices that comprise a computer
system.
Software refers to:
the instructions that control the hardware.
“Caching” is:
moving information from slower storage to faster storage, where it can be accessed more quickly.
A “bus” is:
a set of parallel “wires” for transferring a set of electrical signals simultaneously.
“vonNeumann architecture” refers to computer architectures that:
store programs in memory, and execute them under the control of the instruction execution cycle.
Inside the computer, machine instructions, memory addresses, numbers, characters, etc., are all represented as:
electrical signals.
In the simple CISC architecture, which register holds:
a. the current machine instruction?
b. the current micro-instruction?
a. The Instruction Register (IR).
b. The Control Register.
What is the first step in the instruction execution cycle?
Fetch the instruction at the address in the Instruction Pointer into the Instruction Register.
What is the second step in the instruction execution cycle?
Increment the Instruction Pointer to point to next instruction.
What is the third step in the instruction execution cycle?
Decode the instruction in the Instruction Register.
What is the fourth step in the instruction execution cycle?
If the instruction requires memory access, determine the memory address, and fetch the operand from memory into a CPU register, or send the operand from a CPU register to memory.
What is the fifth step in the instruction execution cycle?
Execute the instruction.
What is the sixth step in the instruction execution cycle?
Repeat from step 1.
Consider the virtual machine levels. At each level (except 0: Digital Logic and 5: High level language), an interpreter accepts an instruction from the level above, converts the instruction to its own language, and passes the resulting instructions to the level below. Note that Level-0 has no interpreter; the instructions from the Micro-architecture level are sent directly to the hardware.
Suppose that the interpreters at each level (levels 1 - 4) generate n instructions in order to represent one instruction from the level above. Suppose also that each Level-0 instruction executes in c nanoseconds.
a. How long does it take to execute a Level-3 instruction?
b. How long does it take to execute a Level-5 instruction?
a. cn^2 ns. Going from level-3 to level-2 creates n instructions. For each of those n instructions, going from level-2 to level-1 creates n instructions, so there will be n^2 micro-instructions, each of which requires c nano-seconds to execute.
b. cn^4 ns.
a. A MASM program must have a procedure named “main.”
b. ‘END main’ is a directive that tells the OS where to begin execution of the program.
a. True
b. True
What's wrong with the following data segment? .data x_value DWORD 5 7Eleven BYTE "My job", 0 X_VALUE DWORD 500 Age ;user's age; DWORD ?
x_value and X_VALUE are the same variable, since MASM is not case-sensitive.
7Eleven is an invalid variable name (can’t start with a digit).
Age ;user’s age; DWORD ? The first semi-colon makes all of the rest of the line into a comment.
The following data segment starts at memory address 1400. What is the address of each variable? .data a. myName BYTE "Elmer Fudd", 0 b. yourName BYTE 30 DUP(0) c. myAge DWORD 45 d. yourAGE DWORD ? e. myScore DWORD ? f. yourScore DWORD ?
a. Address = 1400, size = 11
b. Address = 1400 + 11 = 1411, size = 30
c. Address = 1411+ 30 = 1441, size = 4
d. Address = 1441+ 4 = 1445, size = 4
e. Address = 1445+ 4 = 1449, size = 4
f. Address = 1449+ 4 = 1453, size = 4
How many bits in 35 MiB ?
35 x 2^20 (Bytes) x 8 (bits per Byte) = 293 601 280 bits
What is the width of the internal bus for IA-32 architecture?
32 bits
What is the size of the general-purpose registers for IA-32 architecture?
32 bits
What’s the result of the following code fragment? I.E., what registers are changed?
mov eax, 100
cdq ; convert double to quad
mov ebx, 13
div ebx
Registers changed:
eax contains 7 (integer quotient of 100/13)
ebx contains 13 (assigned, unchanged by division)
edx contains 9 (integer remainder of 100/13)
Given the following constant definition and data segment: MY_CREDITS = 12 .data x DWORD 12 y DWORD 13 z WORD 25
What’s wrong with the following code segment statements?
a. mov ebx, z
b. mov y, x
c. mov ebx, MY_CREDITS
d. mov MY_CREDITS, ebx
a. Size mismatch
b. Can’t move memory to memory
c. Nothing wrong here
d. Can’t assign register to a constant
Given the following data segment: .data intro_1 BYTE "Welcome, " userName BYTE "Fred." intro_2 BYTE "What's up?" count DWORD 0
What is displayed by the following code segment statements? mov edx, OFFSET intro_1 CALL WriteString CALL CrLf mov edx,OFFSET userName CALL WriteString CALL CrLf mov edx, OFFSET intro_2 CALL WriteString CALL CrLf
Welcome, Fred.What’s up?
Fred.What’s up?
What’s up?
Each call to WriteString displays memory until a zero is encountered.
Which two registers are automatically used by integer multiplication and division instructions?
EAX and EDX
Which register is automatically used as a counter for some looping instructions?
ECX
Which register is used for referencing the system stack?
ESP
Most register instructions (for now) reference:
EAX, EBX, ECX, EDX
There is more than one set of registers for the integer unit.
False
Is AL a valid 8-bit register reference?
Yes, AL refers to the 8 low-order bits of EAX
Is DH a valid 8-bit register reference?
Yes, DH refers to the 8 high-order bits of the 16 low-order bits of EDX.
Is SH a valid 8-bit register reference?
No, SH is not allowed. This would be ambiguous, because we have ESP, ESI, and SS registers.