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COMP 2721: Comp Architecture > Week 1, 2 Terms (Quiz 1) > Flashcards

Week 1, 2 Terms (Quiz 1) Flashcards

1
Q

(Class 1) What is a bus?

A

The communication system that transfers data between components inside a computer.

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2
Q

(Class 1) What is a bit?

A

A combination of “bit” and “digit”. It is the smallest unit of information and consists of two logic states: on (1) or off (0).

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3
Q

(Class 1) What is a byte?

A

A unit of information that usually consists of eight bits.

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4
Q

(Class 1) What is a word?

A

The unit of data used by a particular processor design. In a 32-bit system, the size of the word – and the size of the registers – are 32 bits; in a 64-bit system, the word and registers are 64 bits.

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5
Q

(Class 1) What is a register?

A

One of the small data-holding places in a CPU. This is where data is accessed and written to by the CPU.

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6
Q

(Class 1) What is the CPU?

A

The Central Processing Unit executes the instructions of a computer program. It uses the Fetch-Decode-Execute (FDE) cycle.

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7
Q

(Class 1) What is RAM?

A

Random Access Memory (RAM) is a bucket where data can be stored and accessed for the short-term.

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8
Q

(Class 1) What is translation?

A

When a higher-level language is converted to a lower-level language all at once; the original program is thrown out, and the converted program is loaded into memory and executed.

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9
Q

(Class 1) What is interpretation?

A

When a higher-level program is converted to a lower-level program line-by-line and executed immediately.

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10
Q

(Class 1) What are the six levels of a multi-level computer?

A

L5: Problem-Oriented Language (translated via compiler)
L4: Assembly (translated via assembler)
L3: Operating System Machine (partial interpretation, if ISA or not)
L2: Instruction Set Architecture (interpreted or run on hardware)
L1: Microarchitecture
L0: Digital Logic (hardware)

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11
Q

(Class 1) What are the primary powers of 10, and what do they represent?

A

2^10 = kilo (1,000)
2^20 = mega (1,000,000)
2^30 = giga (1,000,000,000)
2^40 = tera (1,000,000,000,000)

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12
Q

(Lab 1) What does RISC stand for? What does it mean?

A

Reduced Instruction Set Computer. It means to issue fewer, and less complex, instructions.

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13
Q

(Lab 1) What are the Design Principles in Modern Computers?

A

(1) All instructions are directly executed by hardware
(2) Maximize the rate at which instructions are issued
(3) Instructions should be easy to decode
(4) Only LOADS and STORES should reference memory
(5) Provide plenty of registers

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14
Q

(Lab 1) What does CISC stand for? What does it mean?

A

Complex Instruction Set Computer. It has more, and more complex, instructions. Implement the most common instructions into hardware.

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15
Q

(Lab 1) What does it mean that “all instructions are executed directly on hardware?”

A

If you can eliminate a level of conversion – translation or interpretation – and instead run those instruction directly on hardware, you’ll speed up a system.

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16
Q

(Lab 1) What does it mean to “maximize the rate at which instructions are issued”?

A

The goal is to create a processor that issues as many instructions per second as possible (which is different to how quickly each issue instruction takes to execute).

17
Q

(Lab 1) What does it mean that “instructions should be easy to decode”?

A

A lot of time and processing power is needed to decode an instruction and determine the resources needed to execute the instruction. Simplifying instructions, and regulating the size and organization of instructions, can increase the speed of this process.

18
Q

(Lab 1) What does it mean that “only LOADS and STORES instructions should reference memory”?

A

Use separate instructions for loading and storing operands from and into memory and for operating on operands. Operation instructions should ONLY occur for operands stored in registers, since this is many times faster than referencing operands in memory.

19
Q

(Lab 1) What is a clock (in a CPU, say?)

A

Anything that turns on or off. In a CPU, the clock is fluctuation between voltage levels at fixed intervals.

20
Q

(Lab 1) What is a CPU clock speed / frequency?

A

How many clock cycles a CPU can perform in one second. We measure this in Gigahertz (one billion Hertz per second).

Some instructions take more than one clock cycle to complete!

21
Q

(Class 2) What is a datapath?

A

A set of functional units that carry out data processing operations. These are located inside a computer’s CPU.

22
Q

(Class 2) What is a program counter?

A

A program counter is a special register that contains the MEMORY ADDRESS of the NEXT instruction to be fetched, decoded, and executed by the CPU.

23
Q

(Class 2) What is the instruction register?

A

The instruction register HOLDS the fetched instruction, which will be subsequently decoded and executed.

24
Q

(Class 2) What is the ALU?

A

The ALU is the Arithmetic Logic Unit. It contains arithmetic and logic operations that it can use on operands.

25
Q

(Class 2) What is temporal locality?

A

Temporal locality assumes that instructions that have been requested are likely to be requested again.

26
Q

(Class 2) What is spatial locality?

A

Spatial locality assumes that the instructions you’re going to need are located in close physical proximity to one another.

27
Q

(Class 2) What is a cache miss?

A

When the CPU requests a word, the cache does not contain that word, so the cache pulls a bunch of addresses from main memory and stores them.

28
Q

(Class 2) What is a pipeline?

A

A set of MULTIPLE HARDWARE DEVICES that fetches, decodes, and executes instructions in PARALLEL and SERIES to maximize INSTRUCTION BANDWIDTH.

29
Q

(Class 2) What is instructional latency?

A

The total time, from start to finish, for ONE instruction to pass through a pipeline. (Add up all the time it takes in all stages, and this will give you the latency.)

Measured in TIME-PER-INSTRUCTION.

30
Q

(Class 2) What is instructional bandwidth?

A

The number of instructions that are fetch, decoded, and executed per unit time.

31
Q

(Class 2) What is a bottleneck?

A

Whenever an instruction moves from a faster-to-slower stage, resulting in a queue. (For example, moving from stage that takes 1 nanosecond to one that takes 2 nanoseconds.)

32
Q

(Class 2) What is super-scalar architecture?

A

Adding extra hardware at the SLOWEST stages in the pipeline, in PARALLEL, to eliminate bottlenecks.

33
Q

(Class 2) What would be the result of deepening a pipeline (adding more but shorter stages)?

A

The latency would stay the same, but the bandwidth would increase.

COMP 2721: Comp Architecture (4 decks)

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