Virtual memory prefetching

Question 1

Prefetching

Answer 1

Predict what data might be needed soon and request for it earlier. If done well, it should reduce memory access latency.

Question 2

Prefetching is only effective under certain conditions. What are they?

Answer 2

There is spare memory bandwidth so the number of memory accesses.

The prefetched memory will be used soon. The prefect prediction is accurate.

The prefetch is done in a timely manner, not too late.

Prefetching doesn’t evict memory in the cache.

Question 3

Software examples to perform prefetching

Answer 3

arrange data structures so access to values are in sequential order or in large intervals

Question 4

Does a compiler add prefetch instructions?

Answer 4

Yes, it is able to optimise by adding prefetch instructions into the program.

Question 5

What is the structure for virtual memory?

Answer 5

Virtual address goes into the MMU (mapping table) and returns a mapped address in physical memory like a disk.

Question 6

MMU

Answer 6

memory management unit

Question 7

Page tables

Answer 7

The mapping of virtual memory to physical memory is saved in page tables because there is a lot of mappings. Page tables. are saved in the L1 cache.

Question 8

TLB (Translation Lookaside Buffer)

Answer 8

a hardware cache for page table entries to reduce access to the page table in memory.

Question 9

What happens when there is a miss at the page table?

Answer 9

The MMU triggers a page fault. The OS page fault handler takes over. It evicts the victim page. If the page is dirty aka it has been modified, it is paged out to the disk. A new page with a new value is added to the page table

Question 10

Why do we add a TLB after having PTE?

Answer 10

Accessing the PTE will cause a 1 cycle delay. So the cost to access PTE is double of normal.

Question 11

TLB reach

Answer 11

the maximum amount of memory the TLB can hold.
Size of TLB size x (size of PTE) or L1.
If every entry in the buffer is replaced with a value in the PTE.

Question 12

Working set

Answer 12

active virtual pages

Question 13

Working set > main memory size what happens?

Answer 13

Main memory is the L1 cache where PTEs are stored. If the working set is more than main memory, then there will need to be accesses to the disk. Its called thrashing and it really increases memory access latency

Question 14

No. of working set pages > No. of TLB entries

Answer 14

The TLB won’t be able to cache all the active pages. So it will need to have TLB misses.