VHDL LAB

Question 1

What is the first thing we do in a VHDL code? Apart from the libraries

Answer 1

We create an entity that defines the external interface to the VHDL component
-defining the inputs and outputs

Question 2

What does the labcounter VHDL do?

Answer 2

-Counts the number of rising edges on the clock.
-when the counter reaches 10, an internak signal called timer_flag is raised
-When the switch is Low the tick_count increases by 1
-The output of the tick_count is a binary number that is equal to a multiple of the 10 rising edges of the clk input

Question 3

What is the key difference between the testbench and design code

Answer 3

The testbench doesn’t need to be converted into hardware logic. (non - synthesised)

Question 4

What does the architecture of the test bench contain?

Answer 4

An instantiation of the design under test (DUT). In the lab a component instantiation is used.