Verilog

Question 1

Implicit nets

wire [2:0] a, c;
assign a = 3’b101;
assign b = a;
assign c = b;
my_module i1 (d,e);

where error in above lines.

Answer 1

Implicit nets
Implicit nets are often a source of hard-to-detect bugs. In Verilog, net-type signals can be implicitly created by an assign statement or by attaching something undeclared to a module port. Implicit nets are always one-bit wires and causes bugs if you had intended to use a vector. Disabling creation of implicit nets can be done using the `default_nettype none directive.

wire [2:0] a, c; // Two vectors
assign a = 3’b101; // a = 101
assign b = a; // b = 1 implicitly-created wire
assign c = b; // c = 001 <– bug
my_module i1 (d,e); // d and e are implicitly one-bit wide if not declared.
// This could be a bug if the port was intended to be a vector.

Adding `default_nettype none would make the second line of code an error, which makes the bug more visible.

Question 2

what does || and | do? which is bitwise and which is logical?

Answer 2

and
|| is logical which means it only checks for 0 or non-zero

is bitwise which means for vectors a[3:0] and b[3:0]

Question 3

input [15:0] in;
output [23:0] out;
assign {out[7:0], out[15:8]} = in;
assign out[15:0] = {in[7:0], in[15:8]};
assign out = {in[7:0], in[15:8]};

Answer 3

input [15:0] in;
output [23:0] out;
assign {out[7:0], out[15:8]} = in; // Swap two bytes. Right side and left side are both 16-bit vectors.
assign out[15:0] = {in[7:0], in[15:8]}; // This is the same thing.
assign out = {in[7:0], in[15:8]}; // This is different. The 16-bit vector on the right is extended to
// match the 24-bit vector on the left, so out[23:16] are zero.
// In the first two examples, out[23:16] are not assigned.

Question 4

how to do case statements?

Answer 4

always @(*) begin // This is a combinational circuit
case (in)
1’b1: begin
out = 1’b1; // begin-end if >1 statement
end
1’b0: out = 1’b0;
default: out = 1’bx;
endcase
end

Question 5

what is casez?

Answer 5

always @(*) begin
casez (in[3:0])
4’bzzz1: out = 0; // in[3:1] can be anything
4’bzz1z: out = 1;
4’bz1zz: out = 2;
4’b1zzz: out = 3;
default: out = 0;
endcase
end

Question 6

A 2-to-1 multiplexer between a and b selected by sel. using conditional operator

Answer 6

(sel ? b : a)

Question 7

A T-flip-flop. using always and conditional operator

Answer 7

always @(posedge clk)
q <= toggle ? ~q : q;

Question 8

State transition logic for a one-input FSM

Answer 8

always @(*)
case (state)
A: next = w ? B : A;
B: next = w ? A : B;
endcase

Question 9

A tri-state buffer using conditinoal operator

Answer 9

assign out = ena ? q : 1’bz;

Question 10

A 3-to-1 mux using conditional operator

Answer 10

((sel[1:0] == 2’h0) ? a : (sel[1:0] == 2’h1) ? b : c )

Question 11

Given a 100-bit input vector [99:0], reverse its bit ordering.

Module Declaration
module top_module(
input [99:0] in,
output [99:0] out
);

Answer 11

module top_module (
input [99:0] in,
output reg [99:0] out
);

always @(*) begin
	for (int i=0;i<$bits(out);i++)		// $bits() is a system function that returns the width of a signal.
		out[i] = in[$bits(out)-i-1];	// $bits(out) is 100 because out is 100 bits wide.
end

endmodule

Question 12

how to use generate block to create a csa adder using full adders?

Answer 12

module full_adder(input in1, input in2, input cin, output carry, output sum);
wire [1:0] carry_and_sum;
always @* begin
carry_and_sum = in1+in2+cin;
sum = carry_and_sum[0];
carry = carry_and_sum[1];
end
endmodule

module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );

genvar i;
generate
    for (i = 0; i < 100; i = i + 1) begin : adders
        if (i == 0) full_adder fa(a[i], b[i], cin, cout[i], sum[i]);
        else full_adder fa(a[i], b[i], cout[i-1], cout[i], sum[i]);
    end
endgenerate endmodule