Unit02: Computer Architecture Flashcards

1
Q

CD-ROM

A

Compact Disk Read-Only Memory

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2
Q

TFT

A

thin film transistor

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3
Q

MB

A

Megabyte

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4
Q

GHz

A

Gigahertz

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5
Q

FSB

A

front-side bus

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6
Q

SDRAM

A

Synchronous Dynamic Random Access Memory

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7
Q

XGA

A

External Graphics Array

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8
Q

SVGA

A

Super Video Graphics Array

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9
Q

AGP

A

Advanced Graphics Port

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10
Q

What is memory size of computer ?

A

RAM

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11
Q

mouse ?

A

control the cursor

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12
Q

clock

A

controls the timing of signals in the computer

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13
Q

RAM

A

holds data read or written to it by the processor

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14
Q

ROM

A

holds intructions which are needed to start up the computer

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15
Q

cache

A

provides extrememly fast access for sections of a program and its data

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16
Q

flash memory key

A

read and writes electronic chips on a card

17
Q

main causes of a PC not running at its highest

A

the time it takes to move data in and out of memory

18
Q

word instead of ‘buffer’

A

cache

19
Q

what devices look after cache coherency

A

cache controller

20
Q

alternative to ‘write-through cache’ ?

A

‘write-back’ cache

21
Q

when ‘write-back’ cache write its content back to main memory

A

‘dirty’…

before using the space to cache new data.

22
Q

When data is marked as ‘dirty’ in ‘write-back’ cache ?

A

Cache entries that have changed are flagged as ‘dirty’ (When data in the cache is changed)

23
Q

What determines what data is replaced in a disk cache ?

A

An algorithm

24
Q

cache hit

A

the processor is succesful in finding the data in cache

25
Q

cache controller

A

the logic circuits used to control the cache process

26
Q

cache coherency

A

ensuring that any changes wrtten to main memory are reflected within the cache and vice versa.

27
Q

wirte-thorugh cache

A

the process of writing directly to both the cache and main memory at the same time.

28
Q

write-back cache

A

the process of writing changes only to the cache and not to main memory unless the cache is used to cache new data.

29
Q

Line size

A

the amount of data transfered to the cache at any one time

30
Q

write-back cache require more inteligent cache controller (TRUE/FALSE)

A

TRUE