UNIT 3 COA

Question 1

I/O subsystem and examples

Answer 1

aka peripheral
eff mode of comm: central sys -> outside enviro
M:cl K P S
(master key paints school)
monitor
kbd
printer
storage device

Question 2

I/O interface need

Answer 2

COST
conversion of sig maybe

synch mech: transfer rate of peri slower than cpu

data codes+formats diff in word formats -> cpu, memory

operating modes of peri diff->peri control no deisturb others to cpu

(io has registers to help out)

special h/w comp bw cpu + peripheral
supervise and synch i/o transfers

Question 3

I/O bus

Answer 3

DAC
data
address
control
(diag 1)

Question 4

Interface modules

Answer 4

SICRI
SCSI
IDE
centronics
rs-232
ieee-488

Question 5

I/O Commands

Answer 5

COSI
Control->io read, give contro; sig to io
output
status->io ready?
input->initialize inp

Question 6

io bus vs memory bus

Answer 6

iop->separate busses for mem and io

memory->same bus, diff control lines:(io read,write mem read,write)
iso i/o or i/o mapped i/o

memory->same bus,same control lines:(some loc -> mem, some loc-> io devices, if these ranges we know which)
mem-map io

Question 7

comp bus?

Answer 7

comm with memory and io

Question 8

example of io

Answer 8

(diag 2)
processor side -> bus buffer
chip select -> which device interface
register select -> which register?

Question 9

modes of transfer

Answer 9

to and from peripherals (io -> cpu, io -> memory)
PID
programmed -> cpu
interrupt initiated -> cpu
dma -> memory

Question 10

programmed io

Answer 10

io -> cpu
program for io -> instructions in program

(diag 3)
data valid active, if data on io bus

interface: data to dr in interface + set flag(io data in dr) in interface

enables data accepted line
io device waits for data accepted acknowdgement to place next data on bus

cpu part(diag 4)
status, flag -> 0 data not ready
flag -> 1 keeps on reading and transfering to memory, if op not done again and againnnn
DISADV: continous monitor(instradd of moving on) flag bit only when 1, continue

Question 11

interrupt initiated io

Answer 11

interrupt to cpu when ready (io data ready) and tells which device as well, no waiting

nonvectored -> fixed branch address -> isr

vectored -> interrupt source(kbd, mouse) gives branch address (direct isr) of int vector

Question 12

io routines

Answer 12

sw routines control peri and transfer data processor -> peri
standard -> manu
in os
in os procedures

Question 13

priority interrupt

Answer 13

many interrupts, identify source and determine first
sw -> polling
hw -> daisy chaining, parallel priority

Question 14

polling

Answer 14

identify highest priority sw
one common branch for all interrupts->polls in sequence(one by one to see, you want interrupt?)->highest priority tested first
DISADVANTAGE: alllll the device checking,exceed time to service device

Question 15

daisy chain

Answer 15

(diag 5)
highest priority -> next highest …->lowest
device sends interrupt request to cpu directly
cpu sends interrupt acknowledgement to first device, pi = 1, if that device, po=0
vad(vector address) placed on data bus to go to cpu (isr)
cpu executes isr

(diag 6 and 7)in each device

Question 16

parallel priority

Answer 16

(diag 8) -> priority encoder -> Io highest pri

(diag 9)
0 -> highest pri
4 devices -> 4 bit register
mask register: don’t want from one input, mask it, enable mask bit to 0
mask bit 1,interrupt bit 1-> 1 to encoder
priority encoder:up ones 0, lower dc
output:vad of isr 00 01 (4 -> 2, 8 -> 3(xyz)…remaining bits = 0
IEN>set/clear to allow interrupts by program
IST->set/clear to allow interrupts by encoder output
enabled -> data bus
after each cycle IEN, IST check

Question 17

nested interrupts

Answer 17

(diag 10 + 9instru)

1. kbd interrupt 749
2. +1 in stack, 750
3. check vad ad goes to that location

Question 18

isr operations

Answer 18

initial:C^2SSP
final:CRCSR
(diag 11)

Question 19

DMA

Answer 19

io -> memory directly
initial:cpu
(diag 12)
(diag 13)
disk  wants direct to memory
dmac:dma request->cpu:bus request->cpu:bus grant->dmac:dma acknowledgement->io:direct transfer(io word in data bus, dmac address to address, less word count when word = 0, eot, else checks requests)

(diag 14)

1. burst: block
2. cycle stealing transfer: byte

Ex. 2000 bytes disk -> memory
part adress to stor in mem (starting address) -> address
control -> byte or block, io to io..
word count:how many?
dma
eot

USES: fast transfer -> mag disks to memory
updating display for interactive terminal, transfer to screen periodically