results from the ALU are stored here - rather than writing working data back to slow memory , processors have several locations of super fast memory called registers that are used to temporarily store results - processor is then able it immediately access and re0use these results in subsequent calcs (add 2+3+4) - for simplicity we will assume the processor has a single general purpose register called an accumulator

UNIT 1: Components of a computer and their uses Flashcards by Federico Orlando

what does CPU stand for

Central processing unit

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What is the Central Processing Unit (CPU)

the processor (also called the central processing unit or cpu) has a number of different components each with their own role to perform:

control unit
buses
arithmetic logic unit (ALU)
dedicated registers

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What is the Control Unit (CU)

the part of the processor that coordinates the activity of all other components

control signals are sent along the control bus between the control unit and the other componenets of the computer

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what is a bus?

Buses in a computer consist of a series of connectors that transfer signals between internal components

they typicaly consist of 8,16,32 or 64 lines

The components of a computer system are connected together using buses. A bus is a communication system that allows internal components to communicate with each other and exchange data.

Each bus consists of a set of parallel — not single — lines along which data can travel. Multiple lines means that multiple bits can travel at the same time allowing data to be transferred quickly between components.

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System bus

the system bus consists of three separate buses carrying control signals, address and data (the big 3)

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name the BIG 3 (buses)

address

data

control

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control signals can include

memory read - data from addressed location in RAM to be placed on the data bus

memeory write - data on the data bus to be written into the addressed location in RAM

bus request - indicates that a device is requesting use of the data bus

bus grant - indicates that the CPU has granted access to the data bus

clock - used to synchronise operations

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Address bus purpose

Carries address locations of stored data from the processor to main memory and input/output controllers

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Data bus purpose

Carries data to and from the processor, main memory, and input/output controllers

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Control Bus purpose

Carries signals that coordinate the operation of the components

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Arithmetic Logic Unit (ALU)

the problem solving part of the processer

perofmrs arithmetic logical and shift operations on data
arithmetic operations - Add, subtract, multiply, divide
logical operations - ADD OR NOT XOR
shift operations: move bits to the left or right within a register

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the accumulator

results from the ALU are stored here

rather than writing working data back to slow memory , processors have several locations of super fast memory called registers that are used to temporarily store results
processor is then able it immediately access and re0use these results in subsequent calcs (add 2+3+4)
for simplicity we will assume the processor has a single general purpose register called an accumulator

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executing instructions (where info is stored)

carrying out a sequence of programming instructions requires many different pieces of information to be held
the processor has to temporarily hold the current instruction being executed
it has to hold the address of the data that it needs and also the data itself
it has to keep track of the address of the next instruction to be executed

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dedicated registers

CIR

MAR

MDR

ACCUMULATOR

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Program counter (PC)

holds the memory address of the next instruction to be executed

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Current Instruction Register (CIR)

holds the current instruction which is split into opcode and operand

Memory address register (MAR)

holds the address in memory where the processor is required to fetch or store data from or to

Memory data register (MDR)

temporarily holds data moving between the processor and main memory

accumulator

to hold intermediate results of an instruction

Fetch Decode Execute Cycle

The fetch-decode-execute cycle describes the basic operation of modern computer systems.

To run a program these instructions must be fetched, decoded, and executed.

They are repeated over and over again for every instruction of every program that is run inside a computer.

Fetch: Steps 1- 4 NAME STEP 1

the address….
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

Fetch: Steps 1- 4 NAME STEP 2

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction…
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

Fetch: Steps 1- 4 NAME STEP 3

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents…
The contents of the MDR are copied to the Current Instruction Register (CIR)

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

Fetch: Steps 1- 4 NAME STEP 4

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents…
The contents…

the address of the next instruction is copied from the PC to the memory address register (MAR)
The instruction held at that address is copied to the Memory Data Register (MDR)
Simultaneously, the contents of the Program Counter (PC) are incremented
The contents of the MDR are copied to the Current Instruction Register (CIR)

Decode: steps 5 - 7 NAME STEP 5 5. The instruction.... 6. It is split into Operand and Opcode to determine the type of instruction it is. Additional data, if required is fetched from memory 7. and passed to the accumulator - the opcode specifies the operation that is to be carried out - the operand holds either: address of the data to be used, which is then copied to the MAR or the actual data to be operated on which is then passed to the MDR

Decode: steps 5 - 7 5. The instruction held in the CIR is decoded 6. It is split into Operand and Opcode to determine the type of instruction it is. Additional data, if required is fetched from memory 7. and passed to the accumulator - the opcode specifies the operation that is to be carried out - the operand holds either: address of the data to be used, which is then copied to the MAR or the actual data to be operated on which is then passed to the MDR

Decode: steps 5 - 7 NAME STEP 6 5. The instruction held in the CIR is decoded 6. It is split into.. 7. and passed to the accumulator - the opcode specifies the operation that is to be carried out - the operand holds either: address of the data to be used, which is then copied to the MAR or the actual data to be operated on which is then passed to the MDR

Decode: steps 5 - 7 NAME STEP 7 5. The instruction held in the CIR is decoded 6. It is split into Operand and Opcode to determine the type of instruction it is. Additional data, if required is fetched from memory 7. and passed to the accumulator: - the opcode specifies .... - the operand holds either...

Execute: step 8 NAME STEP 8

The instruction is executed and the result is held in the accumulator or stored in memory

Words

memory is divided up in equal units called words word length is usually 8,16, 32 or 64 bits each word has a separate memory addressa

address bus in more detail

width of the address bus determines the maximum possible memory addresses of the system with an 8 bit address bus, the max number of addresses is 2^8 (256) an average PC has a memory capacity of 4 GiB (gibi bytes) which 2^32 bytes therefore it must have a 32 bit address bus basically the width of the bus determiens how much memory it has if the pc has 4 GiB memory capacity which is 2^32 bytes it must have a 32 bit address bus for some reason

Data bus in more detail

the data bus is bi directional as data can be sent both ways along the bus - the width of the data is defined by the number of wires or lines it contains if the data bus is the same width as a computer word, data can be transferred to and from memory in a single operation

format of instructions (assembly and machine stuff)

assembly language is very closely related to machine code - generally a one to one correspondance the architecture of a computer including - the word size and the width of the address bus determine the format of machine code instruction for a particular type of processor