Topic 2: Computational Organisation Flashcards
CPU
The key component of a computer system, which contains the circuit necessary to fetch, decode and execute program instructions from and to main memory (RAM). It contains ALU, CU and registers.
CU
Directs the operation of the CPU and the data flow and is in charge of decoding the instructions.
MAR
Temporary storage that stores the memory address from which data will be sent the CPU, or the address to which data will be sent and stored.
ALU
Does all the arithmetic and logical calculations
MDR
Temporary storage that holds data being transferred to and from the RAM.
RAM and properties
Contains the data and instructions the computer has loaded since starting up and everything the user has opened. Those instructions are the ones that the computer has to execute.
- Volatile
- CPU can directly access RAM
- Linked to the CPU by buses
ROM and properties
Used to storage data that is rarely changed such us firmware. It also holds the BIOS (Basic Input/Output)
- Non volatile
- Read only
- The CPU can not directly access the ROM memory.
Cache
A type of small, high-speed memory used to hold frequently used data, so that the CPU needs to access the much slower RAM less frequently. It acts as a buffer between RAM and CPU.
Bus
Communication system that transfers data between components inside a computer, or between computers.
Address bus
Pathway from memory to processing unit carrying the memory address to and from where data is transferred
Importance of both RAM and ROM
RAM and ROM both are the necessary memory for the computer. ROM is a necessary for a computer to boot up. RAM is important for CPU processing.
CPU cycle: Fetch, decode and execute
Fetch
The Program Counter (PC) starts at 0000. This means that the first address in RAM where the computer will look for an instruction is at 0000.
The computer needs somewhere to store the current address in RAM that it is looking for. This is what the Memory Address Register (MAR) is for. 0000 is therefore copied into the MAR.
As the data fetched during the fetch stage is an instruction, it is copied into the Instruction Register (IR).
As the first instruction has been fetched, the system is at the end of the Fetch stage of the cycle. The program counter can be incremented by 1, so the system is ready to read the next instruction when the next Fetch cycle starts.
Decode
Now the instruction needs to be decoded. It is sent via the data bus to the control unit, where it is split into two parts.
The first part is the operation code or opcode, which in this example CPU is the first 4 bits. This is the command that the computer will carry out. The second part, in this case the second 4 bits, is the operand.
This is an address in RAM where data will be read from or written to, depending on the operation. The Control Unit can translate opcodes into instructions. So here the Control Unit translates the opcode 0101 into an instruction, for example LOAD FROM RAM.
Execute
Now the command will be executed. The operand is copied to the MAR, as this is the address of the data that needs to be loaded.
The data at address is then fetched from RAM and passed up the data bus to the MDR. As it is not an instruction but simply data, it is then passed to the Accumulator (Acc).
Types of RAM
Static and dynamic
Types of ROM
PROM: Can be programmed by user)
EPROM: Can be reprogrammed
EEPROM: Can be erased
Hard Drive Disk
Storage device that uses mechanical platters moving read/write head to access data.