Term 1 Flashcards
What is the difference between a structural and behavioural description?
Structural - tells us how we would make it but not what it would do e.g. an Ikea construction leaflet
Behavioural - tells us what the design should do but not how to make it e.g. g <= ‘1’ when a>b else ‘0’;
VHDL can be written in both
What does the ENTITY declaration describe?
Creates the port map used to determine signals going in and out of a module
What is the ARCHITECTURE?
Describes how the outputs respond to the inputs –> the function of the module
What is the difference between:
i) a: STD_LOGIC_VECTOR (0 TO 3)
ii) a: STD_LOGC_VECTOR (3 DOWNTO 0)
i) 0110 MSB 0110
What are local signals and how are they declared?
Used to define the internal connections in a module, between internal logic gates. They cannot be accessed by the rest of the system.
ARCHITECTURE number3 OF full add IS
SIGNAL n1, n2, n3, n4: STD_LOGIC;
How is the following code processed? (nX are signals) n1 <= x XOR y; sum <= cin XOR n1; n2 <= x AND y; n3 <= cin AND x; n4 <= y AND cin; cout <= n2 OR n3 OR n4;
- All statements are scanned simultaneously
- Whenever a signal on the RHS changes (also called an event) the relevant statement will run, computing new values
- This may trigger more RHS signals to change, which are then processed AFTER the initial events have finished processing
- This continues until there are no more events to process
Does the order of code matter in VHDL? Are there any exceptions?
Normally, all statements are monitored at the same time so the order doesn’t matter –> concurrent execution
The exception to this is when a PROCESS is used, then the code inside the process is executed sequentially.
Signals have their values frozen while a process is running.
How does a structural description look in VHDL? How is it run?
Architecture structural OF fulladd IS
SIGNAL n1, n2, n3: STD_LOGIC;
BEGIN
g1: ENTITY work.xor2(simple) PORT MAP (x, y, n1);
g2: ENTITY work.xor2(simple) PORT MAP (n1, cin, sum);
g3: ENTITY work.xor2(simple) PORT MAP (x, y, n2);
etc.
All statements are scanned simultaneously like before, waiting for an event on an input signal (same as behavioural)
How is a delay used in VHDL? What is the smallest interval of time that can be used?
By using the AFTER function (can be used to simulate gates having a small delay between input and output)
Delta - meaning a ‘moment’
Construct the event queue for an example in the lecture notes: 4-3
Answer in lecture notes
What is inertial delay?
If the inputs of a gate changes to produce an output pulse that is shorter than the gate delay, the output pulse never happens and the output of the gate remains constant.
What is concatenation?
Merges two vectors to produce a longer vector
Is an IF block executed sequentially? Where can it be used?
Yes, as such it can only be used inside a process
What is the general code for setting something to trigger on a clock edge?
PROCESS (clk)
BEGIN
IF ( rising_edge(clk) ) THEN
q <= d;
END IF;
END PROCESS;What is the purpose of including d-type flip flops (or registers) into a circuit?
To clean up glitches that occur when an output changes to an undesired value (see 6-6/6-7/6-8 for examples). The d-type delays the output by a clock cycle.
What is Register Transfer Level coding (RTL)?
Using data flow statements but wrapping them up in processes triggered by a clock or another signal (e.g. reset). Still simply defining the desired behaviour.
How are variables different to signals?
A variable can only exist inside a process -> declared between PROCESS and BEGIN statements. The assignments of values to variables take effect immediately:
process (clk)
variable b: STD_LOGIC_VECTOR (3 down 0);
begin
if (rising_edge(clk)) then
b := c;
a <= b;
end if;
end process;
b gets the value of c straight away (when inside a clocked process) –> imagine a wire being drawn
What is a sensitivity list?
Used when declaring a process, if one of the signals in the sensitivity list changes then the process is run.
What are the desirable features of the CMOS logic family?
High speed
Low power consumption
Low cost
Ability to pack a high density of gates on a single chip
What are the 2 most important types of MOSFETs?
n-channel: d<=s (gate closed) when g=1
p-channel: d<=s (gate closed) when g=0
