Structure and Function of the Processor Flashcards
What is the ALU?
The ALU (Arithmetic and Logic Unit) completes all of the arithmetical and logical operations. Arithmetical operations include all mathematical operations such as addition and subtraction on fixed or floating point numbers. Logical operations include boolean logic operations such as AND, OR, NOT, and XOR.
What is the control unit?
The Control Unit is the component of the processor which directs the operations of the
CPU. It has the following jobs: -
Controlling and coordinating the activities of the CPU —-
Managing the flow of data between the CPU and other devices
Accepting the next instruction
Decoding instructions
Storing the resulting data back in memory
what is a register
Registers
Registers are small memory cells that operate at a very high speed. They are used to
temporarily store data and all arithmetic, logical and shift operations occur in these
registers.
job of the program counter
holds address of next instruction to be executed
job of accumulator
Stores the results from calculations
job of memory address reg
Holds the address of a location that is to be
read from or written to.
job of mem address reg
Temporarily stores data that has been read
or data that needs to be written.
job of current instruction reg
Holds the current instruction being
executed, divided up into operand and
opcode.
width of bus
The width of the bus is the number of parallel wires the bus has. The width of the bus is
directly proportional to the number of bits that can be transferred simultaneously at any
given time. buses are typically 8, 16, 32 or 64 wires wide.
what are buses
Buses are a set of parallel wires which connect two or more components inside the CPU.
There are three buses in the CPU: data bus, control bus, and address bus. These buses
collectively are called the system bus.
data bus
This is a bi-directional bus (meaning bits can be carried in both directions). This is used for
transporting data and instructions between components.
control bus
This is a bi-directional bus used to transmit control signals between internal and external
components. The control bus coordinates the use of the address and data buses and
provides status information between system components.
address bus
This is the bus used to transmit the memory addresses specifying where data is to be sent
to or retrieved from. The width of the address bus is proportional to the number of
addressable memory locations.
control signals of control bus
bus request: shows that a device is requesting the use of the data bus —–
Bus grant: shows that the CPU has granted access to the data bus
Memory write: data is written into the addressed location using this bus
Memory read: data is read from a specific location to be placed onto the data bus,
Interrupt request: shows that a device is requesting access to the CPU
Clock: used to synchronise operations
assembly language
Assembly code uses mnemonics to represent instructions,
for example ADD represents addition. This is a simplified
way of representing machine code.
The instruction is divided into operand and opcode in the
Current Instruction Register. The operand contains the data
or the address of the data upon which the operation is to be
performed. The opcode specifies the type of instruction to
be executed.
A LEVEL ONLY - PIPELINING
Pipelining is the process of completing the fetch, decode, and execute cycles of three
separate instructions simultaneously, holding appropriate data in a buffer in close proximity
to the CPU until it’s required. While one instruction is being executed, another can be
decoded and another fetched.
what is fetch decode eecute cycle
The fetch-decode-execute cycle is the sequence of operations that are completed in order
to execute an instruction.
aim of pipelining - A LEVEL ONLY
Pipelining is aimed to reduce the amount of the CPU which is kept idle. It is separated into
instruction pipelining and arithmetic pipelining. Instruction pipelining is separating out the
instruction into fetching, decoding, and executing. Arithmetic pipelining is breaking down
the arithmetic operations and overlapping them as they are performed.
decode phase
Decode phase: -
The contents of CIR are split into operand and opcode
the data/instruction is decoded and processed
fetch phase
Fetch phase: -
Address from the PC is copied to the MAR —
Instruction held at that address is copied to MDR by the data bus
Simultaneously, the contents of the PC are increased by 1
The value held in the MDR is copied to the CIR
amount and type of cache mem
Cache memory is the CPU’s onboard memory. Instructions fetched from main memory are
copied to the cache, so if required again, they can be accessed quicker. As cache fills up,
unused instructions are replaced.
execute phase
Execute phase: -
The decoded instruction is executed
lev 2 cache
Relatively fast memory cell, with a medium
sized capacity. (256KB-2MB)
num of cores
A core is an independent processor that is able to run its own fetch-execute cycle. A
computer with multiple cores can complete more than one fetch-execute cycle at any given
time. A computer with dual cores can theoretically complete tasks twice as fast as a
computer with a single core. However, not all programs are able to utilise multiple cores
efficiently as they have not been designed to do so, so this is not always possible.
factors affecting cpu performace
There are three factors that affect CPU performance: clock speed, number of cores and
the amount and type of cache memory.
clock speed
The clock speed is determined by the system clock. This is an electronic device which
generates signals, switching between 0 and 1. All processor activities begin on a clock
pulse, and each CPU operation starts as the clock changes from 0 to 1. The clock speed is
the time taken for one clock cycle to complete.
lev 1 cache
Very fast memory cells with a small
capacity. (2-64KB)
von neumann architecture
This architecture includes the basic components of the computer and processor (single
control unit, ALU, registers and memory units) in which a shared memory and shared data
bus is used for both data and instructions. Von Neumann architecture is built on the stored
program concept.
