Structure and Function of Processor Flashcards
What is a Register?
Extremely fast form of storage within the CPU to temporarily store small amounts of data as the CPU processes that data, with some having a specific purpose
What is the ALU?
Arithmetic Logic Unit and performs arithmetic and logical operations
What is the CU?
Control Unit which coordinates the input and output devices connected to the computer to execute the instructions and control the flow of signals within the buses
What is the PC?
Program Counter and stores the address of the next instruction that will be fetched and increments after
What is the Accumulator?
Temporarily stores the outputs of the ALU
What is the MAR?
Temporarily stores the address of the next instruction to be fetched from main memory through the address bus
What is the MDR?
Temporarily stores a copy of the data or instruction that was fetched from the main memory address that was pointed to by the MAR
What is the CIR?
Current Instruction Register that holds the current instruction, ready to be decoded`
What are busses?
A communication system within the CPU that transmits data between the registers and other computer components
What is the Data Bus?
Carries data instruction around the systen
What is the Address Bus?
Carries memory address from the MAR to main memory
What is the Control bus?
Carries signals from the CU to coordinate inputs and outputs around the system
What is the Clock?
With each tick of the clock, an instruction is processed
What are the steps in the Fetch-Decode-Execute cycle?
- The PC stores the address of the next instruction to be fetched, copied it into the MAR and increments the PC, which will point to the next instruction
- The instruction found at the address the MAR has pointed to is copied to the MDR from main memory
- The instruction from the MDR is copied to the CIR
- The CU decodes the contents of the CIR and executed the instructions by sending signals to the relevant components
Name the 6 main factors explaining CPU performance
Clock Speed, No. of Cores, Cache, RAM Capcity, GPU, Pipelining