SR LATCH STUDY

Question 1

What is an SR Latch?

Answer 1

An SR Latch is a memory device created by connecting two logic gates (NAND or NOR) with feedback loops, allowing it to maintain a state based on its inputs.

Question 2

Describe the inputs and outputs of an active-low SR latch using NAND gates.

Answer 2

Inputs: S (Set) and R (Reset); Outputs: Q (normal) and Q’ (inverse). Q = 1 when set, and Q = 0 when reset. Q’ is the inverse of Q.

Question 3

What is an “active low” SR latch?

Answer 3

It’s a latch that activates with a 0 input. In the active-low SR latch, a 0 on S sets the latch, and a 0 on R resets it.

Question 4

What is the critical race condition in SR latches?

Answer 4

It’s an oscillation caused when both inputs (S and R) are de-asserted at exactly the same time, potentially leaving the latch’s next state undefined.

Question 5

Explain the truth table for an SR latch (NAND, Active Low) when S=1, R=1.

Answer 5

When S=1 and R=1, the latch retains its previous state.

Question 6

Describe the behavior of a NOR gate SR latch (active high).

Answer 6

For a NOR SR latch, S and R inputs are active high, meaning S=1 sets the latch, and R=1 resets it.

Question 7

What does an SR latch with enable do?

Answer 7

The enable (E) input allows or disables the SR latch’s response to S and R inputs. When E=0, the latch ignores input changes.

Question 8

What is the output when both S and R are active in a NAND SR latch with enable?

Answer 8

In a NAND SR latch with enable, both Q and Q’ will be 1 when S=R=1, while in NOR, both Q and Q’ will be 0.

Question 9

How does the timing diagram illustrate SR latch states?

Answer 9

The timing diagram shows changes in Q and Q’ over time as S and R inputs change, indicating when the latch is in set or reset states.