SPIN, Exokernel, Microkernel Flashcards
What are the overall characteristics of a microkernel?
- Provides abstractions to resources/OS core services
- Each service is its own address space
- Microkernel serves as the middleman between services and OS services
What are the downsides of microkernels?
- Potential for performance loss due to extra border crossings from services to OS service
- High communication overhead
Goals of extensibility
To be able to be:
- Thin like microkernel
- Access to resources without border crossings
- Flexible
Previous approaches to extensibility
- HydraOS
- Microkernels
- Cross domain communication
- Little languages
What was SPIN’s approach to extensibility?
Use language features to extend OS
Language used was Modula-3
What are the characteristics of SPIN?
- Kernel is minimal, but extendable (avoids border crossings)
- Compiler enforces modularity
- Logical protection domains (not hardware address space)
- Dynamic call binding (ensures flexibility)
How is SPIN customizable?
- Defines interfaces to subsystems
- Just need to specify: start, create, resolve, combine
What are SPIN extensions?
- Pieces of code that reside above SPIN
- Definitions of interfaces to subsystems
- Customizable
What are program discontinuities?
- Page fault
- External interrupts
- System calls
- Exceptions
How does SPIN handle program discontinuities?
Passes program discontinuities to library OS as events through event handlers/procedure calls
Doing so avoid context switches
What do core services do in SPIN?
- Provide access to hardware mechanisms
- Does involve stepping outside the language to control hardware resources
What are core services in SPIN?
- Memory management (physical, virtual, translation)
- CPU scheduling (app level, processor level, global)
What sorts of services does SPIN require definition for for memory management?
- Physical: allocate, deallocate, reclaim
- Virtual: allocate, deallocate
- Translation: create/destroy address space, add/remove mapping
What sorts of services does SPIN require definition for for CPU management?
- Strand: abstraction for scheduler entity defined by app thread package
- Event handlers: block/unblock, checkpoint, resume
- Global scheduler: interacts with app thread packages
How does SPIN handle protection?
Through extensions. Extensions to core services only affect the applications that use the extension
What does SPIN achieve in terms of extensibility, protection and performance?
- Achieves as good performance as monolithic OS
- Is flexible/extendible
What is Exokernel’s approach to extensibility?
Uncouples authorization from use
How does Exokernel achieve extensibility?
Secure bindings:
- Library OS asks for hardware resource
- Exokernel binds library OS to hardware resource
- Exokernel exposes hardware resource to library OS via encrypted key
How are Exokernel secure bindings implemented?
- Hardware mechanisms (TLB entry)
- Software caching (shadow TLB)
- Downloading code directly into the kernel
How does software caching work within the context of Exokernel?
Each library OS has a “shadow” TLB to reduce start up penalty
How does Exokernel handle memory management?
- Uses shadow TLB
- Loads STLB into hardware TCB to help with context switches
- If TCB is warm, it will not miss as often
How does Exokernel handle CPU scheduling?
- Uses a linear vector of “time slots”
- Time quantum (how long each process can be on processor)
- OS calls a time slot and runs processes for that time slot according to the time quantum
How does Exokernel revoke resources?
- Via software interrupt from Exokernel (uses a repossession vector)
- Library OS allowed to do back up work to write data to disk prior to repossession
How often do addresses get translated in Exokernel?
On every memory access on CPU
The CPU deals with translating virtual addresses to physical addresses
How does Exokernel mitigate border crossings?
Can download code into the kernel
Effect: selectively bloats the kernel
How does Exokernel handle events?
- A table in the kernel that maps entry points for different event types to the library OS
- Forwards the events to library OS
What metrics are used for performance comparisons?
- System size
- Microbenchmarks
- Networking
- Application level performance
What is the difference between SPIN and Exokernel?
- SPIN is an OS
- Exokernel is neither a microkernel nor an OS
- Exokernel can be written in any language
- In SPIN, entire OS is in same hardware space with kernel level privileges
- In Exokernel, selected code fragments are downloaded into kernel by library OS via secure bindings
How does Exokernel and SPIN do in terms of performance comparisons?
- Code size is small
- Performs as well as monolithic OS
- Protected procedure calls do as well as sys calls in Unix
What was the purpose of the L3 Microkernel Construction paper?
To prove that microkernels could be efficient if implemented correctly
What are the characteristics of a microkernel-based OS?
- Each services exists in its own address space
- Services are above the microkernel
- Microkernel gets its own address space
- Provides simple abstractions for system services, resources
Where can performance be potentially lost in a microkernel?
- Border crossings
- Protected procedure calls
What are myths about the microkernel that made it “underperform”?
- Kernel-user space switches
- Address space switches (basis for protected procedure calls)
- Thread switches and IPC (kernel mediation for protected procedure call)
- Memory effects (locality loss)
How does L3 Microkernel do in terms of performance with border crossings?
Including TLB and cache misses, takes about 123 processor cycles
How does L3 Microkernel deal with address space switches?
- Don’t have to flush the TLB completely
- Check address space tag and PID for matches (if no address space tag, can use segment registers)
- Can share hardware address space for protection domains (segment boundaries enforced by hardware)
- Good for small protection domains (must flush for large)
What is the explicit cost for flushing TLB?
The cost of flushing the registers and flushing the TLB
What is the implicit cost for flushing TLB?
After switching, trying to access previous memory
What is the working set?
The set of pages that keeps the process happy
Why do we have to flush the TLB completely for large protection domains?
- implicit cost»_space; explicit cost
- Switching cost not as important
How does L3 Microkernel deal with thread switching and IPC?
By construction, competitive to SPIN and Exokernel
Saves volatile state of processor
How does L3 Microkernel deal with memory effects?
Hardware address space is bigger than the cache
How does L3 Microkernel compare to MACH?
L3 takes advantage of processor specific features in order to maximize performance
L3 is inherently non-portable as a result
Why is MACH’s border crossings so expensive?
- Focus on portability (longer latency for border crossings)
- Code bloat (large memory footprint)
- System cache misses dominate
- Capacity misses dominate
- Kernel footprint is the culprit, not system services
What did modern OSes learn from SPIN, Exokernel and L3 Microkernel?
- Modern OSes adopted microkernel
- Dynamic loading of device drivers come from extensibility lessons
- Virtualization is based off of extensibility
- It is possible to get protection, performance and extensibility
What are the benefits of SPIN?
- Logical protection domains enforced by strongly typed language
- Applications can dynamically bind to different implementations (provides flexibility)
What are the drawbacks of SPIN?
- Lots of third party vendors that don’t always use the same language
- Drivers for hardware access must be accessed outside of the language protection
What is contained in the Exokernel shadow TLB?
- Guaranteed VM to PM mappings.
- On context switch, associated S-TLB is loaded into hardware TLB
How does Exokernel service a page fault?
- Invokes handler registered for library OS in Processor Environment data structure
- Library OS finds free page frame, runs page replacement algorithm
- Library OS calls its hard disk driver to initiate I/O from disk to physical page frame
- Device driver presents capability to Exokernel for Direct Memory Access
- Once DMA has been completed, Exokernel upcalls library OS using PE
- Library OS updates mapping in TLB
- If valid, Exokernel installs mapping and resumes
How does Exokernel handle external interrupts?
- Uses Time Slice vector to identify library OS responsible for handling
- Every library OS has a Processor Environment data structure with entry points for interrupt handling
- Every device driver can identify OS it needs to alert
- If process to be interrupted is not running, is queued up
- When processor runs, Exokernel will deliver interrupt by upcalling registered interrupt context entry point to OS
How do we avoid flushing the TLB during Address Space Switches?
- Provide unique address space IDs to each subsystem so that the address space tagged TLB can be exploited
- Use kernel threads and hand off scheduling between subsystems to implement protector procedure calls between subsystems
- Provide efficient memory sharing mechanisms across subsystems so copying overhead is reduced during protected procedure call
