SLR1 Flashcards
What is the fetch decode execute cycle?
The cycle which is carried out by the processor to complete jobs to run a computer.
Explain the fetch section of the FDE cycle.
The PC stores the address of the next instruction to be fetched from the RAM. This is the copied into the MAR (Memory Address Register). Next, a signal is sent across the address bus to the RAM and a memory read signal from the control unit is sent across the control bus to the RAM. The value of at the address stored in the MAR is found in the RAM and is sent across the data bus and stored in the MDR (Memory Data Register). After this, the value is sent to the CIR (Current Instruction Register) if the value is an instruction; otherwise it is sent to the ACCUMULATOR to be used in a calculation. If it is an instruction, it is copied from the CIR to the DECODE UNIT and decoded.
Explain the decode section of the FDE cycle.
The DECODE UNIT reads the operand which is the first 4 bits of the binary value as it tells the processor what needs to be done to the value. For example, 0001 could relate to LOAD in the instruction set of the processor. This means that the final 4 bits of the value represent the address of where more data needs to be loaded from. This second of part of the binary value is called the opcode.
Explain the execute section of the FDE cycle.
Depending on the operand, the execute section carries out whatever task needs to be carried out. For example, it could be storing a value in an address, loading a value from the RAM, adding two numbers or branching.
What is meant by the term “branching”?
Branching is when the code jumps from one line to a line that is not the following line if a condition is triggered. In LMC, the triggers for branching could be if the value is zero (BRZ), if the value is positive (BRP), or branch always (BRA).
Instruction set of LMC.
LDA - Load STA - Store ADD - Addition SUB - Subtract INP - Input OUT - Output DAT - Data Location BRZ - Branch if zero BRA - Branch always BRP - Branch if positive HLT - Halt/Stop
What three factors affects the performance of the processor?
Clock speed Bus width Cache Memory Registers RAM
How does the RAM affect the processor’s performance?
If the RAM is large, it can store a large amount of instructions which means the access speeds from teh processor are quicker. If the RAM is smaller, then the instructions have to be stored in virtual memory which is in secondary storage. As the file transfer speeds to secondary storage are slower, less instructions can be accessed per second so the performance of the processor is slower. There is a direct correlation between the size of the RAM and the performance of the processor.
How does the clock speed affect the processor’s performance?
The system clock is used to synchronise the cylces in the processor. Therefore, if the clock is faster, more cycles can be carried out per second, resulting in the processor performing better. The system clock cycles are measured in Hertz (Hz) and the average speed is around 2.5 GHz which means 2.5 billion cycles are carried out per second.
How does the Bus width affect the processor’s performance?
The bigger the bus width, the greater the number of instructions and values that can be transferred between the RAM and the processor.
How does cache memory affect the processor’s performance?
The cache memory is memory that is within the CPU that stores teh most recent instructions. The access speeds to the cache memory is even aster than RAM which makes the size of the cache memory greatly affect hte processor’s performance. The bigger the cache memory, the better the performance of the CPU as more cycles can be carried out per second as the instructions can be accessed quicker.
How do the registers affect the processor’s performance?
The registers store the binary values of the FDE cycle. This means that as the size of the registers increase, so does the number of values that can be stored in them. The average processor has 32-bit registers meaning they can store 4 binary values at a time.
What is pipelining?
Pipelining is a process which increases the efficiency of the CPU as when one job has been fetched and is being decoded, the second job is fetched to ensure that there are no idle parts of the processor. This means that the processor can complete more cycles per second which makes it more efficient. Pipelining is an example of parallel processing.
What is the problem with pipelining?
Programs have branches in them so the processor has to use ‘predictive pipelining’ which predicts when the program is going to branch. If the processor gets this wrong and the program doesn’t do as the processor expects it to, then the pipelines have to be emptied (flushed) which worsens the performance of the processor as it has wasted time fetching and decoding the other instructions.
What are features of the Von Neumann Architecture?
Shared memory space for instructions and data.
Instructions and data are stored in the same format.
One process at a time.
A single control unit follows a linear FDE cycle.
Registers are used as fast access to instructions and data.
Served by the system bus.
