Semiconductors Flashcards

1
Q

Describe and draw the band gaps for conductors, insulators and semi conductors

A

Conductors - overlapping energy bands = easy e- movement
Insulators - big band gap between bonding and anti bonding = hard e- movement
SC- medium gap (1.2Ev Si) between conduction and valence band

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2
Q

Why can’t e- be excited to the antibonding energy band in insulators but can to the conduction band in SC?

A

Because of the size of the energy band = amount of energy required
e- only start moving between the band in extreme conditions in insulators

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3
Q

Are band gaps a continuous size?

A

They change across the length of the band gap (no effect on large band gaps) due to orientations in the crystal and energetic effects.
e- will take the lowest energy path to bridge a band gap, so they don’t always travel straight upwards (resulting in direct and indirect band gaps)

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4
Q

Draw a direct and an indirect band gap and explain what an e- needs to be promoted

A

Direct - two semi circles separated by gap, e- needs to absorb a photon
Indirect - two semi circles that are off centre, need a photon and a phonon to move across the band gap

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5
Q

What is meant by intrinsic semiconductor?

A

Undoped semiconductor, a material with a medium band gap (roughly 1Ev) that means an e- needs to be excited to move across the band gap

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6
Q

What happens when an electron is promoted from the valence band to the conduction band?

A

A hole is left in the valence band, this is also mobile

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7
Q

Name two intrinsic semi conductors

A

Ge and Si (both have 4 valence e-)

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8
Q

What is Ni in intrinsic semi conductors and what’s it effected by?

A

Ni is the number of intrinsic charge carriers per volume, = Nh = Ne-
- more thermal and photon excitation = more carriers

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9
Q

How many Ni are created in a semi conductor?

A

Production rate = species . e^band gap/k.temp
K= Boltzmann constant
Steady state is achieved when production = recombination

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10
Q

How can the density of charge carriers be worked out?

A

Nh . Ne = Ni2

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11
Q

What dictates the conductivity of a semiconductor?

A

Ni, their charge and their velocity
e- have a higher mobility than holes = e- are the majority charge carriers = higher effect on conductivity
Conductivity = e.(μh.Nh+ μe.Ne)
e = charge, μ = mobility

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12
Q

Why do intrinsic semiconductors need to be doped?

A

Because Ni production rate is negligible at room temp, doping increasing the number of Ni and thus the conductivity

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13
Q

Explain p-type doping

A
  • Dope with an element in a lower group
  • this atoms valence band sits just above the SC valence band
  • e- promoted to this valence band = mobile hole in valence band
  • means that Nh = dopant level and that Nh doesn’t = Ne, but Ni2 = Nh.Ne
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14
Q

Explain n-type doping

A
  • doping with a group above the SC
  • sits just below the conduction band
  • e- excited from the dopant to the conduction band and is then mobile
  • means Ne = dopant level and increases conductivity more than p-type doping
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15
Q

What affects conductivity more - P-type or N-type doping?

A

N-type because e- are majority carriers and e- are much more mobile than holes = bigger affect on conductivity

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16
Q

How do defects effect conductivity?

A

They act as e- traps meaning that Ne is reduced = reduced conductivity

17
Q

What material properties do semiconductors need?

A
Single crystal/very large grains due to defects trapping e- 
Very pure (also due to defects)
18
Q

How is pure Si produced?

A

Quartzite is reduced to coke to yield 97% pure Si, electric arc furnace used to purify Si to 99.999%

19
Q

Explain the Czochralski process

A

Si crucible surrounded with graphite (to conduct from heater to crucible) filled with molten Si (1500°)
Seed dips into rotating pool of Si, rotating the other way (to reduce defects), seed pulls large single crystal boule from melt, argon gas passed around to remove gas contaminants, annealing also occurs as at hot temps

20
Q

How do you change Czochralski Si into electrical grade Si?

A

Needs purification (zone refinement)

  • bottom of Si boule is re-melted and then molten zone moved up through material
  • impurities are rejected into melt pool by solidifying Si and move to top of boule (this is rejected at end)
21
Q

What happens to the Czochralski boule after purification?

A

Cut into brittle thin wafers, which are then polished (electrical discharge machining to minimise defect addition), then dopant diffused into material (after purification or dopants would be removed)

22
Q

How is Si doped?

A

Wafers places into quartz furnace, surrounded by dopant gas and heated (as increase diffusion rate), then gas removed and heating continues so diffusion continues and composition profile is removed (as surface dopant no longer being replaced)

23
Q

Draw the fermi levels of intrinsic and extrinsic semiconductors

A

Intrinsic - line from left side of conduction to right side of valence (Ef in middle)
Extrinsic - line from dopant to nearest band (Ef in middle), p-type Ef < n-type Ef

24
Q

What is a PN junction?

A

It’s when a p-type and n-type semiconductor are joined

Most useful applications of semiconductors require a PN junction

25
Q

What happens to the fermi level at a PN junction

A

Ef equilibrate (like a thermocouple) by e- movement through the depletion zone

26
Q

Draw a PN junction

A

P-type higher than N-type, Ef are equal, with depletion zone containing + from N-type and - from P-type

27
Q

What happens at the depletion zone of a PN junction?

A

e- and holes recombine and emit a photon with energy = band gap
This only occurs when there is an applied field which causes movement

28
Q

Explain forward bias

A

Forward bias - when field is applied from P-type to N-type (+ve at P-type, -ve at n-type), this moves e- from n-type (where they are majority carrier) to the depletion zone and holes from the p-type (majority carriers) to depletion zone
Lots of recombination

29
Q

Explain reverse bias

A

Field applied from p-type to n-type, causes hole and e- to move away from the depletion zone so very little recombination occurs (still some due to minority carriers moving)

30
Q

How can reverse and forward bias be used in application?

A

Leds will only emit light in one direction because of this (where light = band gap energy)

31
Q

Describe molecular beam epitaxy

A

heated Krudsen effusion cells release elements into the vacuum which condense on rotating substrate, slow rate so atoms mitigate across substrate if ionic/covalently bonded - forms single crystal
Mass spectrometer checks air comp and X-ray diffraction (source & detector) to measure substrate size)

32
Q

Why are metals difficult to MBE

A

Metallically bonded - don’t mitigate across substrate and don’t grow epitaxially

33
Q

What is a MOSFET?

A

Metal oxide semiconductor field effect transistor - used to store memory in bits as 1 or 0

34
Q

Describe the structure of a MOSFET

A

Source, gate and drain on an oxide insulator (n+ type below gate an drain) sitting on top of p-type slab - contact on bottom

35
Q

Describe how a MOSFET works

A

Charge is distributed across metal-oxide-p-type junction, Fe balanced = changing metal Ef affects Ef in Ptype -ve voltage = rise in Ef = majority carrier accumulation at interface. +ve Pd causes inversion and depletion region in p-type near n+ regions = e- can move from source to drain = data storage and movement

36
Q

What is the job of the gate in MOSFETS?

A

Input of charge through gate control source voltage
Inversion = accumulation of minority carriers at interface - +ve cause inversion for p-type, -ve for n-type (as pushes majority carriers away)

37
Q

How does a USB store data?

A

Uses a floating point MOSFET as increases accuracy and control by using control gate and floating gate

38
Q

Why is gate alignment crucial in MOSFETS?

A

Too much overlap or incomplete overlap prevents flow of charge = MOSFET stops working
Solved by using self-aligning gates (male source and drain after gate)

39
Q

Describe the production process for floating point MOSFETS, with self aligning gates

A

P-type, SiO2 layer on top, Sputter on gate (etch excess away using mask), ion implantation to add n+ region, heat SiO2 to grow insulation over and around gate
SiO2 removed from top of gate and n+
Metal sputtered to form drain and source