Semiconductor Technology Flashcards
What does cMOS stand for?
Complementary Metal Oxide Semiconductor
What is cMOS?
cMOS is a type of technology used in the manufacturing of computer processors, memory chips, and other digital devices
Why is cMOS so widely used?
- High levels of integration
- Small devices
- Large numbers on chip
- → High functionality
- → Low cost/function
- Very low static power
- Only consumes power when switching state
- Portable appliances
What is planar processing?
- Mass production of devices on wafer
- Diffuse dopants into surface
- Grow layers on surface
- Pattern and etch layers
- All devices formed simultaneously
- Complex multi-layer printing process
State suitable materials for an n-type dopant for silicon.
- Phosphine
- Arsine
Group 5
5 valence electrons
Four outer electrons combine with ever one silicon atom, while the fifth electron is free to move and serves as charge carrier.
State a suitable material for an n-type dopant for GaAs.
The n-type dopant must be electron donating, therefore group 6.
- Selenium
- Sulfur
State a suitable material for a p-type dopant for GaAs.
The p-type dopant must be electron accepting, therefore group 2.
- Zinc
- Cadmium
What is GaAs?
Gallium Arsenide
What is the work function for an n-type semiconductor?
WF = IE - E(g)
IE: Ionisation Energy
E(g): Energy Band Gap
What is the work function for a p-type semiconductor?
WF = IE
IE: Ionisation Energy
How do you find the potential difference for a p-n junction?
V(b) = (k(B)T/q) * ln [N(D) * N(A) / n(i)^2]
Where:
* k(B)T/q = 0.026
* N(D) is Donor impurity concentration
* N(A) is Acceptor impurity concentration
* n(i) is intrinsic concentration
How do you find the depletion width of a p-n junction?
d = d(n) + d(p) = ( 2ε(r)ε(0)V(T) / q ) ^(1/2) * ( (1 / N(D)) + (1 / N(A)) ) ^(1/2)
Where:
* d(n) is n-type region
* d(p) is p-type region
- ε(r) is relative permittivity
- ε(0) is vacuum permittivity
- V(T) is total potential difference across the junction
- q is the charge of an electron
What is capacitance per unit area equal to?
C / A = ε(r) * ε(0) / t(0)
Where:
* ε(r) is relative permittivity
* ε(0) is vacuum permittivity
* t(0) is thickness
Describe the diffusion of electrons from the n-type region into the p-type region of a p-n junction at thermal equilibrium.
- Charges flow in each direction due to the concentration gradients.
- The uncompensated donor (acceptor) ions generate a potential difference
- that moves free charges in the opposite direction to the diffusion.
- At equilibrium, there is a region of width, d, that is depleted of free charges.
Suggest dopant materials for n-type lnP.
- Sulfur (S)
- Selenium (Se)
Suggest a dopant material for p-type lnP.
- Zinc (Zn)
Suggest a dopant material for n-type ZnSe.
- Gold (Au)
- Copper (Cu)
Give the equation that describes the chemical reaction that occurs during wet oxidation of silicon.
Si + 2H(2)O -> SiO(2) + 2H(2)
Give the equation that describes the chemical reaction that occurs during dry oxidation of silicon.
Si + O(2) -> SiO(2)
Summarise wet oxidation.
- Temperature 600°C - 1400°C
- Rate varies with temperature and crystal face
- Fast, low quality oxide
Summarise dry oxidation.
- Temperature 600°C - 1400°C
- Slow, high quality oxide
List 4 types of doping methods.
- During crystal growth & deposition
- Diffusion
- Ion implantation
- Transmutation doping
How do you build a cMOS device?
- Put nMOS and pMOS devices on a single substrate
- Use doped well to put pMOS device in
- Use polysilicon gates
- common to both nMOS and pMOS
Why is the channel of a pMOS device typically made 3x wider than the channel width of the corresponding nMOS device when they are used together to form an inverter?
- Mobility of electrons > Mobility of holes
- -> Make p-type devices wider than that of n-type devices
Describe the term “interstitial” in the context of impurities within a crystal.
- Not electrically active
- Distortions in crystal lattice
Describe the term “substitutional” in the context of impurities within a crystal.
- Electrically active
- Little distortions in lattice
Why is an intrinsic semiconductor a poor conductor of electricity?
- Current requires the flow of electrons,
- Semiconductors have their valence bands filled
- Preventing the entry flow of new electrons
State a suitable material for the metal gate electrode in a n-GaAs MESFET.
Polysilicon (polycrystalline)
Describe how an ideal metal - p-type semiconductor Schottky junction is modified by the presence of a thin film oxide layer between the metal and p-type semiconductor.
- Thin insulating layer, such as silicon dioxide, reduces rates of electron-hole pair recombination
- and dark current
- by allowing the possibility of minority carriers to tunnel through this layer
Suggest an application for an ideal metal - p-type semiconductor with a thin film oxide layer.
- Photovoltaic cell
- (thin film oxide layer improve Photovoltaic cell performance)
What is the cause of ‘metal spiking’ in contact regions of devices?
Metal spiking occurs when the metal (aluminium) diffuses into the contact region (e.g. silicon).
Give two techniques that may be used to reduce the effect of ‘metal spiking’.
- Deposit Al/Si alloy instead of pure aluminium
Compromise between:
* Low silicon content -> spiking
* High silicon content -> high resistivity
Explain what happens under the gate of an nMOS capacitor as the potential on the gate is increased from below the threshold voltage V(T), to above the threshold.
- Depletion ( V(FB) < V(g) < V(T) )
- Substrate near gate depleted of charge
- Inversion ( V(g) > V(T) )
- Free electrons pulled into substrate near gate
- Inversion (n-type) layer forms - channel
What is the energy barrier?
Built-in potential V(B)
How do you find the flat band bias?
V(FB) = Φ(MS) - Q(0) / C(0)
Where:
* Φ is the potential barrier (in V)
* Q(0) is the charge per unit area
* C(0) is the capacitance per unit area
Give an overview of the MOS transistor.
- Voltage operated device
- Voltage on GATE affects current flow in channel between SOURCE and DRAIN
- Source & DRAIN ‘printed’ in surface of wafer
Give the cMOS process flow steps.
- Layer deposition & oxidation
- Doping & dopants
- Lithography & patterning
- Etching & removal of material
How do you find the flatband voltage?
V(FB) = Φ(M) - Φ(S)
Where:
* Φ(M) is the workfunction of metal
* Φ(S) is the workfunction of semiconductor
What does the symbol χ represent?
Electron affinity
How do you find the silicon workfunction for an nMOS device?
Φ(S) = χ + (E(g) / 2q) - V(t) ln (N(a) / n(i) )
Figures for silicon at 300K
χ ≈ 4.05V
E(g) ≈ 1.12 eV
V(t) ≈ 0.026V (kT/q)
ni ≈ 10^10
How do you find the silicon workfunction for a pMOS device?
Φ(S) = χ + (E(g) / 2q) - V(t) ln (N(d) / n(i) )
Figures for silicon at 300K
χ ≈ 4.05V
E(g) ≈ 1.12 eV
V(t) ≈ 0.026V (kT/q)
ni ≈ 10^10
Define the Threshold Voltage V(T).
- As gate potential increases
- More electrons drawn into depletion region
- Significant when electron density ≥ Hole density
- Forms ‘inversion’ layer (n-type)
- Depletion region: Insulating
- Inversion layer: Conducting
