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Engineering Physics Year 3 > Semiconductor Technology > Flashcards

Semiconductor Technology Flashcards

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1
Q

What does cMOS stand for?

A

Complementary Metal Oxide Semiconductor

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2
Q

What is cMOS?

A

cMOS is a type of technology used in the manufacturing of computer processors, memory chips, and other digital devices

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3
Q

Why is cMOS so widely used?

A
  • High levels of integration
  • Small devices
  • Large numbers on chip
  • → High functionality
  • → Low cost/function
  • Very low static power
  • Only consumes power when switching state
  • Portable appliances
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4
Q

What is planar processing?

A
  • Mass production of devices on wafer
  • Diffuse dopants into surface
  • Grow layers on surface
  • Pattern and etch layers
  • All devices formed simultaneously
  • Complex multi-layer printing process
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5
Q

State suitable materials for an n-type dopant for silicon.

A
  • Phosphine
  • Arsine

Group 5
5 valence electrons

Four outer electrons combine with ever one silicon atom, while the fifth electron is free to move and serves as charge carrier.

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6
Q

State a suitable material for an n-type dopant for GaAs.

A

The n-type dopant must be electron donating, therefore group 6.

  • Selenium
  • Sulfur
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7
Q

State a suitable material for a p-type dopant for GaAs.

A

The p-type dopant must be electron accepting, therefore group 2.

  • Zinc
  • Cadmium
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8
Q

What is GaAs?

A

Gallium Arsenide

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9
Q

What is the work function for an n-type semiconductor?

A

WF = IE - E(g)

IE: Ionisation Energy
E(g): Energy Band Gap

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10
Q

What is the work function for a p-type semiconductor?

A

WF = IE

IE: Ionisation Energy

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11
Q

How do you find the potential difference for a p-n junction?

A

V(b) = (k(B)T/q) * ln [N(D) * N(A) / n(i)^2]

Where:
* k(B)T/q = 0.026
* N(D) is Donor impurity concentration
* N(A) is Acceptor impurity concentration
* n(i) is intrinsic concentration

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12
Q

How do you find the depletion width of a p-n junction?

A

d = d(n) + d(p) = ( 2ε(r)ε(0)V(T) / q ) ^(1/2) * ( (1 / N(D)) + (1 / N(A)) ) ^(1/2)

Where:
* d(n) is n-type region
* d(p) is p-type region

  • ε(r) is relative permittivity
  • ε(0) is vacuum permittivity
  • V(T) is total potential difference across the junction
  • q is the charge of an electron
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13
Q

What is capacitance per unit area equal to?

A

C / A = ε(r) * ε(0) / t(0)

Where:
* ε(r) is relative permittivity
* ε(0) is vacuum permittivity
* t(0) is thickness

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14
Q

Describe the diffusion of electrons from the n-type region into the p-type region of a p-n junction at thermal equilibrium.

A
  • Charges flow in each direction due to the concentration gradients.
  • The uncompensated donor (acceptor) ions generate a potential difference
  • that moves free charges in the opposite direction to the diffusion.
  • At equilibrium, there is a region of width, d, that is depleted of free charges.
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15
Q

Suggest dopant materials for n-type lnP.

A
  • Sulfur (S)
  • Selenium (Se)
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16
Q

Suggest a dopant material for p-type lnP.

A
  • Zinc (Zn)
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17
Q

Suggest a dopant material for n-type ZnSe.

A
  • Gold (Au)
  • Copper (Cu)
18
Q

Give the equation that describes the chemical reaction that occurs during wet oxidation of silicon.

A

Si + 2H(2)O -> SiO(2) + 2H(2)

19
Q

Give the equation that describes the chemical reaction that occurs during dry oxidation of silicon.

A

Si + O(2) -> SiO(2)

20
Q

Summarise wet oxidation.

A
  • Temperature 600°C - 1400°C
  • Rate varies with temperature and crystal face
  • Fast, low quality oxide
21
Q

Summarise dry oxidation.

A
  • Temperature 600°C - 1400°C
  • Slow, high quality oxide
22
Q

List 4 types of doping methods.

A
  • During crystal growth & deposition
  • Diffusion
  • Ion implantation
  • Transmutation doping
23
Q

How do you build a cMOS device?

A
  • Put nMOS and pMOS devices on a single substrate
  • Use doped well to put pMOS device in
  • Use polysilicon gates
  • common to both nMOS and pMOS
24
Q

Why is the channel of a pMOS device typically made 3x wider than the channel width of the corresponding nMOS device when they are used together to form an inverter?

A
  • Mobility of electrons > Mobility of holes
  • -> Make p-type devices wider than that of n-type devices
25
Q

Describe the term “interstitial” in the context of impurities within a crystal.

A
  • Not electrically active
  • Distortions in crystal lattice
26
Q

Describe the term “substitutional” in the context of impurities within a crystal.

A
  • Electrically active
  • Little distortions in lattice
27
Q

Why is an intrinsic semiconductor a poor conductor of electricity?

A
  • Current requires the flow of electrons,
  • Semiconductors have their valence bands filled
  • Preventing the entry flow of new electrons
28
Q

State a suitable material for the metal gate electrode in a n-GaAs MESFET.

A

Polysilicon (polycrystalline)

29
Q

Describe how an ideal metal - p-type semiconductor Schottky junction is modified by the presence of a thin film oxide layer between the metal and p-type semiconductor.

A
  • Thin insulating layer, such as silicon dioxide, reduces rates of electron-hole pair recombination
  • and dark current
  • by allowing the possibility of minority carriers to tunnel through this layer
30
Q

Suggest an application for an ideal metal - p-type semiconductor with a thin film oxide layer.

A
  • Photovoltaic cell
  • (thin film oxide layer improve Photovoltaic cell performance)
31
Q

What is the cause of ‘metal spiking’ in contact regions of devices?

A

Metal spiking occurs when the metal (aluminium) diffuses into the contact region (e.g. silicon).

32
Q

Give two techniques that may be used to reduce the effect of ‘metal spiking’.

A
  • Deposit Al/Si alloy instead of pure aluminium

Compromise between:
* Low silicon content -> spiking
* High silicon content -> high resistivity

33
Q

Explain what happens under the gate of an nMOS capacitor as the potential on the gate is increased from below the threshold voltage V(T), to above the threshold.

A
  • Depletion ( V(FB) < V(g) < V(T) )
  • Substrate near gate depleted of charge
  • Inversion ( V(g) > V(T) )
  • Free electrons pulled into substrate near gate
  • Inversion (n-type) layer forms - channel
34
Q

What is the energy barrier?

A

Built-in potential V(B)

35
Q

How do you find the flat band bias?

A

V(FB) = Φ(MS) - Q(0) / C(0)

Where:
* Φ is the potential barrier (in V)
* Q(0) is the charge per unit area
* C(0) is the capacitance per unit area

36
Q

Give an overview of the MOS transistor.

A
  • Voltage operated device
  • Voltage on GATE affects current flow in channel between SOURCE and DRAIN
  • Source & DRAIN ‘printed’ in surface of wafer
37
Q

Give the cMOS process flow steps.

A
  • Layer deposition & oxidation
  • Doping & dopants
  • Lithography & patterning
  • Etching & removal of material
38
Q

How do you find the flatband voltage?

A

V(FB) = Φ(M) - Φ(S)

Where:
* Φ(M) is the workfunction of metal
* Φ(S) is the workfunction of semiconductor

39
Q

What does the symbol χ represent?

A

Electron affinity

40
Q

How do you find the silicon workfunction for an nMOS device?

A

Φ(S) = χ + (E(g) / 2q) - V(t) ln (N(a) / n(i) )

Figures for silicon at 300K
χ ≈ 4.05V
E(g) ≈ 1.12 eV
V(t) ≈ 0.026V (kT/q)
ni ≈ 10^10

41
Q

How do you find the silicon workfunction for a pMOS device?

A

Φ(S) = χ + (E(g) / 2q) - V(t) ln (N(d) / n(i) )

Figures for silicon at 300K
χ ≈ 4.05V
E(g) ≈ 1.12 eV
V(t) ≈ 0.026V (kT/q)
ni ≈ 10^10

42
Q

Define the Threshold Voltage V(T).

A
  • As gate potential increases
  • More electrons drawn into depletion region
  • Significant when electron density ≥ Hole density
  • Forms ‘inversion’ layer (n-type)
  • Depletion region: Insulating
  • Inversion layer: Conducting

Engineering Physics Year 3 (5 decks)

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